10

Maxim Integrated

18-Bit, Single-Channel, Ultra-Low Power, Delta-

Sigma ADC with 2-Wire Serial Interface

MAX11212

Data Read Following Every Conversion

The MAX11212 indicates conversion data availabil-

ity as well as allows the retrieval of data through the

RDY/DOUT output. The RDY/DOUT output idles at the

value of the last bit read unless a 25th SCLK pulse is

provided, causing RDY/DOUT to idle high. RDY/DOUT is

pulled low when the conversion data is available.

Figure 1 shows the timing diagram for the data read.

Once a low is detected on RDY/DOUT, clock pulses at

SCLK clock out the data. Data is shifted out MSB first

and is in binary two’s complement format. Once all the

data has been shifted out, a 25th SCLK is required to

pull the RDY/DOUT output back to the idle high state.

See Figure 2.

If the data is not read before the next conversion data is

updated, the old data is lost, as the new data overwrites

the old value.

Data Read Followed by Self-Calibration

To initiate self-calibration at the end of a data read,

provide a 26th SCLK pulse. After reading the 16 bits of

conversion data, a 25th positive edge on SCLK pulls

the RDY/DOUT output back high, indicating end of data

read. Provide a 26th SCLK pulse to initiate a self-calibra-

tion routine starting on the falling edge of the 26th SCLK.

A subsequent falling edge of RDY/DOUT indicates data

availability at the end of calibration. The timing is illus-

trated in Figure 3.

Figure 1. Timing Diagram for Data Read After Conversion

Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK

1

D17

CONVERSION IS DONE

DATA IS AVAILABLE

CONVERSION IS DONE

DATA IS AVAILABLE

D16

0

23

24

SCLK

RDY/DOUT

1

D17

CONVERSION IS DONE

DATA IS AVAILABLE

CONVERSION IS DONE

DATA IS AVAILABLE

D16

0

23

24

25

SCLK

RDY/DOUT

25TH SLK RISING EDGE

PULLS RDY/DOUT

HIGH