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MC68EC040FE33B Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MC68EC040FE33B Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 442 page  viii M68040 USER’S MANUAL MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Section 4 Instruction and Data Caches 4.1 Cache Operation ................................................................................... 4-2 4.2 Cache Management.............................................................................. 4-5 4.3 Caching Modes ..................................................................................... 4-6 4.3.1 Cachable Accesses ........................................................................... 4-6 4.3.1.1 Write-Through Mode ......................................................................4-6 4.3.1.2 Copyback Mode ............................................................................. 4-6 4.3.2 Cache-Inhibited Accesses ................................................................. 4-7 4.3.3 Special Accesses .............................................................................. 4-7 4.4 Cache Protocol ..................................................................................... 4-7 4.4.1 Read Miss ......................................................................................... 4-8 4.4.2 Write Miss .......................................................................................... 4-8 4.4.3 Read Hit ............................................................................................ 4-8 4.4.4 Write Hit ............................................................................................. 4-8 4.5 Cache Coherency ................................................................................. 4-9 4.6 Memory Accesses for Cache Maintenance........................................... 4-11 4.6.1 Cache Filling...................................................................................... 4-11 4.6.2 Cache Pushes ................................................................................... 4-13 4.7 Cache Operation Summary................................................................... 4-13 4.7.1 Instruction Cache............................................................................... 4-14 4.7.2 Data Cache........................................................................................ 4-15 Section 5 Signal Description 5.1 Address Bus (A31–A0) ......................................................................... 5-4 5.2 Data Bus (D31–D0) ...............................................................................5-5 5.3 Transfer Attribute Signals...................................................................... 5-5 5.3.1 Transfer Type (TT1, TT0) .................................................................. 5-5 5.3.2 Transfer Modifier (TM2–TM0) ........................................................... 5-6 5.3.3 Transfer Line Number (TLN1, TLN0)................................................. 5-6 5.3.4 User-Programmable Attributes (UPA1, UPA0) .................................. 5-7 5.3.5 Read/Write (R/W) .............................................................................. 5-7 5.3.6 Transfer Size (SIZ1, SIZ0) ................................................................ 5-7 5.3.7 Lock (LOCK) ...................................................................................... 5-7 5.3.8 Lock End (LOCKE) ............................................................................ 5-7 5.3.9 Cache Inhibit Out (CIOUT) ................................................................ 5-8 5.4 Bus Transfer Control Signals ................................................................ 5-8 5.4.1 Transfer Start (TS) ............................................................................. 5-8 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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