REV. 0

–5–

ADG726/ADG732

Parameter

Unit

Conditions/Comments

0

ns min

CS to WR Setup Time

0

ns min

CS to WR Hold Time

10

ns min

WR Pulsewidth

10

ns min

Time between

WR Cycles

5

ns min

Address, Enable Setup Time

2

ns min

Address, Enable Hold Time

NOTES

Specifications subject to change without notice.

CS

WR

A0, A1, A2, A3, (A4)

EN

Figure 1. Timing Diagram

Figure 1 shows the timing sequence for latching the switch

address and enable inputs. The latches are level sensitive; there-

fore, while

WR is held low, the latches are transparent and the

switches respond to changing the address and enable the inputs.

Input data is latched on the rising edge of

WR. The ADG726

has two

CS inputs. This enables the part to be used either as a

dual 16-1 channel multiplexer or a differential 16-channel

multiplexer. If a differential output is required, tie

CSA and

CSB together.