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MAX6457UKD3B-T Datasheet(PDF) 9 Page - Maxim Integrated Products

Part # MAX6457UKD3B-T
Description  High-Voltage, Low-Current Voltage Monitors in SOT Packages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX6457UKD3B-T Datasheet(HTML) 9 Page - Maxim Integrated Products

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MAX6457–MAX6460
High-Voltage, Low-Current Voltage Monitors in
SOT Packages
9
Maxim Integrated
Hysteresis
Hysteresis adds noise immunity to the voltage monitors
and prevents oscillation due to repeated triggering
when VIN is near the threshold trip voltage. The hystere-
sis in a comparator creates two trip points: one for the
rising input voltage (VTH+) and one for the falling input
voltage (VTH-). These thresholds are shown in Figure 6.
The internal hysteresis options of the MAX6457/
MAX6458/MAX6459 are designed to eliminate the need
for adding an external hysteresis circuit.
Timeout Period
The timeout period (tTP) for the MAX6457 is the time
from when the input (IN+) crosses the rising input
threshold (VTH+) to when the output goes high (see
Figures 6 and 7). For the MAX6458, the monitored volt-
age must be in the “window” before the timeout starts.
The MAX6459 and MAX6460 do not offer the extended
timeout option (150ms). The extended timeout period is
suitable for overvoltage protection applications requir-
ing transient immunity to avoid false output assertion
due to noise spikes.
Latched-Output Operation
The MAX6457 features a digital latch input (CLEAR) to
latch any overvoltage event. If the voltage on IN+ (VIN+)
is below the internal threshold (VTH-), or if VCC is below
4V, OUT remains low regardless of the state of CLEAR.
Drive CLEAR high to latch OUT high when VIN+ exceeds
VTH+. When CLEAR is high, OUT does not deassert if
VIN+ drops back below VIN-. Toggle CLEAR to deassert
OUT. Drive CLEAR low to make the latch transparent
(Figure 7). CLEAR must be low when powering up the
MAX6457. To initiate self-clear at power-up, add a 100k
pullup resistor from CLEAR to VCC and a 1µF capacitor
from CLEAR to GND to hold CLEAR low. Connect
CLEAR to GND when not used. See Figure 9.
IN+
OUT
>VTH+
<VTH-
VCC
VCC
0
0
tTP
tTP
tTP
CLEAR
Figure 7. Timing Diagram (MAX6457)
5-CELL
Li+
BATTERY
STACK
BATTERY
CHARGER
DC-DC
CONVERTER
LOAD
R1
R2
RPULLUP
IN
OUT
+21V
VCC
GND
IN+
OUT
(OUTA FOR
MAX6459)
MAX6457–
MAX6460
SHDN
Figure 8. Undervoltage Lockout Typical Application Circuit


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