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ADSP-2186KST-133 Datasheet(PDF) 5 Page - Analog Devices |
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ADSP-2186KST-133 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 36 page  ADSP-2186 –5– REV. B Pin Terminations (Continued) I/O Hi-Z * Pin 3-State Reset Caused Unused Name (Z) State By Configuration D4 or I/O (Z) Hi-Z BR, EBR Float IS I I High (Inactive) D3 or I/O (Z) Hi-Z BR, EBR Float IACK Float D2:0 or I/O (Z) Hi-Z BR, EBR Float IAD15:13 I/O (Z) Hi-Z IS Float PMS O (Z) O BR, EBR Float DMS O (Z) O BR, EBR Float BMS O (Z) O BR, EBR Float IOMS O (Z) O BR, EBR Float CMS O (Z) O BR, EBR Float RD O (Z) O BR, EBR Float WR O (Z) O BR, EBR Float BR I I High (Inactive) BG O (Z) O EE Float BGH O O Float IRQ2/PF7 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float IRQL1/PF6 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float IRQL0/PF5 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float IRQE/PF4 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float SCLK0 I/O I Input = High or Low, Output = Float RFS0 I/O I High or Low DR0 I I High or Low TFS0 I/O O High or Low DT0 O O Float SCLK1 I/O I Input = High or Low, Output = Float RFS1/ IRQ0 I/O I High or Low DR1/FI I I High or Low TFS1/ IRQ1 I/O O High or Low DT1/FO O O Float EE I I EBR II EBG OO ERESET II EMS OO EINT II ECLK I I ELIN I I ELOUT O O NOTES *Hi-Z = High Impedance. 1. If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register. 2. If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1, and let them float. 3. All bidirectional pins have three-stated outputs. When the pins are configured as an output, the output is Hi-Z (high impedance) when inactive. 4. CLKIN, RESET, and PF3:0 are not included in the table because these pins must be used. Setting Memory Mode Memory Mode selection for the ADSP-2186 is made during chip reset through the use of the Mode C pin. This pin is multi- plexed with the DSP’s PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are passive and active. Passive configuration involves the use of a pull-up or pull-down resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pull-down, on the order of 100 k Ω, can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor’s output driver. For minimum power consumption during power-down, reconfigure PF2 to be an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch. Active configuration involves the use of a three-stateable exter- nal driver connected to the Mode C pin. A driver’s output en- able should be connected to the DSP’s RESET signal such that it only drives the PF2 pin when RESET is active (low). After RESET is deasserted, the driver should three-state, thus allow- ing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a three- stated buffer. This ensures that the pin will be held at a constant level and not oscillate should the three-state driver’s level hover around the logic switching point. Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. The ADSP-2186 provides four dedicated external interrupt input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the PF7:4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FI and FO, for a total of six external interrupts. The ADSP-2186 also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and RESET). The IRQ2, IRQ0 and IRQ1 input pins can be pro- grammed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table I. Table I. Interrupt Priority and Interrupt Vector Addresses Source Of Interrupt Interrupt Vector Address (Hex) Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Power-Down (Nonmaskable) 002C IRQ2 0004 IRQL1 0008 IRQL0 000C SPORT0 Transmit 0010 SPORT0 Receive 0014 IRQE 0018 BDMA Interrupt 001C SPORT1 Transmit or IRQ1 0020 SPORT1 Receive or IRQ0 0024 Timer 0028 (Lowest Priority) |
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