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ADUC7128BSTZ126-RL2 Datasheet(PDF) 10 Page - Analog Devices |
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ADUC7128BSTZ126-RL2 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 92 page  ADuC7128/ADuC7129 Rev. 0 | Page 10 of 92 I2C® Timing Specifications Table 4. I P 2 P C Timing in Fast Mode (400 kHz) Parameter Description Slave Min Slave Max Master Typ Unit tL SCLOCK low pulse width1 200 1360 ns tH SCLOCK high pulse width1 100 1140 ns tSHD Start condition hold time 300 251,350 ns tDSU Data setup time 100 740 ns tDHD Data hold time 0 400 ns tRSU Setup time for repeated start 100 12.51350 ns tPSU Stop condition setup time 100 400 ns tBUF Bus-free time between a stop condition and a start condition 1.3 μs tR Rise time for both SCLOCK and SDATA 100 300 200 ns tF Fall time for both SCLOCK and SDATA 60 300 20 ns tSUP Pulse width of spike suppressed 50 ns 1 tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD. SDATA (I/O) tBUF MSB LSB ACK MSB 1 9 8 2–7 1 SCLOCK (I) PS STOP CONDITION START CONDITION S(R) REPEATED START tSUP tR tF tF tR tH tL tSUP tDSU tDHD tRSU tDHD tDSU tSHD tPSU Figure 5. I P 2 P C-Compatible Interface Timing |
Similar Part No. - ADUC7128BSTZ126-RL2 |
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Similar Description - ADUC7128BSTZ126-RL2 |
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