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ADUC7128BSTZ126-RL2 Datasheet(PDF) 11 Page - Analog Devices

Part # ADUC7128BSTZ126-RL2
Description  Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADUC7128BSTZ126-RL2 Datasheet(HTML) 11 Page - Analog Devices

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ADuC7128/ADuC7129
Rev. 0 | Page 11 of 92
SPI Timing Specifications
Table 5. SPI Master Mode Timing (PHASE Mode = 1)
Parameter
Description
Min
Typ
Max
Unit
tSL
SCLOCK low pulse width1
(SPIDIV + 1) × tHCLK
ns
tSH
SCLOCK high pulse width1
(SPIDIV + 1) × tHCLK
ns
tDAV
Data output valid after SCLOCK edge
2 × tHCLK + 2 × tUCLK
ns
tDSU
Data input setup time before SCLOCK edge2
1 × tUCLK
ns
tDHD
Data input hold time after SCLOCK edge2
2 × tUCLK
ns
tDF
Data output fall time
5
12.5
ns
tDR
Data output rise time
5
12.5
ns
tSR
SCLOCK rise time
5
12.5
ns
tSF
SCLOCK fall time
5
12.5
ns
1 tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MOSI
MSB
BIT 6 TO BIT 1
LSB
MISO
MSB IN
BIT 6 TO BIT 1
LSB IN
tSH
tSL
tSR
tSF
tDR
tDF
tDAV
tDSU
tDHD
Figure 6. SPI Master Mode Timing (PHASE Mode = 1)


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