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ADUC7129BSTZ126-RL2 Datasheet(PDF) 8 Page - Analog Devices |
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ADUC7129BSTZ126-RL2 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 92 page  ADuC7128/ADuC7129 Rev. 0 | Page 8 of 92 TIMING SPECIFICATIONS Table 2. External Memory Write Cycle Parameter Min Typ Max Unit CLK UCLK tMS_AFTER_CLKH 0 4 ns tADDR_AFTER_CLKH 4 8 ns tAE_H_AFTER_MS ½ CLK tAE (XMxPAR[14:12] + 1) × CLK tHOLD_ADDR_AFTER_AE_L ½ CLK + (!XMxPAR[10]) × CLK tHOLD_ADDR_BEFORE_WR_L (!XMxPAR[8]) × CLK tWR_L_AFTER_AE_L ½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK tDATA_AFTER_WR_L 8 12 ns tWR (XMxPAR[7:4] + 1) × CLK tWR_H_AFTER_CLKH 0 4 ns tHOLD_DATA_AFTER_WR_H (!XMxPAR[8]) × CLK tBEN_AFTER_AE_L ½ CLK tRELEASE_MS_AFTER_WR_H (!XMxPAR[8] + 1) × CLK CLK CLK tMS_AFTER_CLKH tAE_H_AFTER_MS tAE tWR_L_AFTER_AE_L MS AE WS RS A/D[15:0] FFFF 9ABC 5678 9ABE 1234 BLE BHE A16 tWR tWR_H_AFTER_CLKH tHOLD_DATA_AFTER_WR_H tHOLD_ADDR_AFTER_AE_L tHOLD_ADDR_BEFORE_WR_L tDATA_AFTER_WR_L tBEN_AFTER_AE_L tADDR_AFTER_CLKH tRELEASE_MS_AFTER_WR_H Figure 3. External Memory Write Cycle |
Similar Part No. - ADUC7129BSTZ126-RL2 |
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Similar Description - ADUC7129BSTZ126-RL2 |
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