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©2012 Fairchild Semiconductor Corporation

FDMQ86530L Rev. C1

Figure 7.

0

5

10

15

20

25

0

2

4

6

8

10

Gate Charge Characteristics

Figure 8.

0.1

1

10

60

1

10

100

1000

10000

f = 1 MHz

Capacitance vs Drain

to Source Voltage

Figure 9.

0.01

0.1

1

10

100 300

0.005

0.01

0.1

1

10

70

DERIVED FROM

TEST DATA

1 ms

10 s

10 ms

DC

1 s

100 ms

THIS AREA IS

LIMITED BY r

DS(on)

SINGLE PULSE

Forward Bias Safe

Operating Area

Figure 10.

10

-4

10

-3

10

-2

10

-1

110

100

1000

0.5

1

10

100

1000

3000

SINGLE PULSE

t, PULSE WIDTH (sec)

Single Pulse Maximum

Power Dissipation

Figure 11. Junction-to-Ambient Transient Thermal Response Curve

10

-4

10

-3

10

-2

10

-1

110

100

1000

0.0001

0.001

0.01

0.1

1

2

SINGLE PULSE

o

C/W

DUTY CYCLE-DESCENDING ORDER

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

NOTES: