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TMC2011AN2C Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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TMC2011AN2C Datasheet(HTML) 4 Page - Fairchild Semiconductor |
4 / 12 page TMC2011A/2111A PRODUCT SPECIFICATION 4 Table 1. Programming Length Controls Pin Descriptions – TMC2111A Pin Name Pin Number Pin Function Description DIP PLCC Power VDD 78 Supply Voltage. The TMC2111A operates from a single +5V supply. All power and ground lines must be connected. GND 17,18 20,21,22 Ground. The TMC2111A operates from a single +5V supply. All power and ground lines must be connected. Data Inputs DI7-0 12,11,10, 9,4,3,2,1 14,13,12, 10,5,4,3,2 Data Input. Eight inputs are provided for the data, which pass through the shift register unchanged. The TMC2111A consists of a single group of eight bits with all data bits having equal delays. Data Outputs DO7-0 13,14,15, 16,21,22, 23,24 15,16,17, 18,26,27, 28,1 Data Output. The outputs of the shift register are delayed relative to the input signals. The amount of the delay is programmable (see Table 1). The outputs remain valid for a minimum of tHO nanoseconds after the leading edge of CLK. This allow the data to be latched into circuits with non-zero hold time requirements. Controls CLK 8 9 Master Clock. All inputs and outputs are synchronous and operate from a single master clock. All operations occur on the rising edge of the master clock. L3-0 19,20,6,5 23,24,7,6 Length Select. The length select input is used to determine the register delay of the TMC2111A. This input is registered and affects the output tDO after the clock edge after it is input to the device (see Timing Diagram). Delay lengths are specified in Table 1. TMC2011A TMC2111A Input Code Mode (MC) =0 Mode (MC) =1 L3 L2 L1 L0 DO3-0 Length DO7-4 Length DO3-0 Length DO7-4 Length DO7-0 Length 0 0 0 0 333 18 1 0 0 0 1 444 18 2 0 0 1 0 555 18 3 0 0 1 1 666 18 4 0 1 0 0 777 18 5 0 1 0 1 888 18 6 0 1 1 0 999 18 7 0 1 1 1 10 10 10 18 8 1 0 0 0 11 11 11 18 9 1 0 0 1 12 12 12 18 10 1 0 1 0 13 13 13 18 11 1 0 1 1 14 14 14 18 12 1 1 0 0 15 15 15 18 13 1 1 0 1 16 16 16 18 14 1 1 1 0 17 17 17 18 15 1 1 1 1 18 18 18 18 16 |
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