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TMC22091KHC Datasheet(PDF) 7 Page - Fairchild Semiconductor |
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TMC22091KHC Datasheet(HTML) 7 Page - Fairchild Semiconductor |
7 / 60 page PRODUCT SPECIFICATION TMC22091/TMC22191 7 Pin Descriptions Pin Name Pin Number Value Pin Function Description 84-Lead PLCC 100-Lead MQFP Clocks PXCK 79 60 TTL Master Clock Input. This 20 to 30 MHz clock is internally divided by 2 to generate the internal pixel clock, PCK, which a LOW on RESET forces LOW. PXCK drives the entire TMC22x91, except the asynchronous microprocessor interface and the semi-synchronous LDV data input clock. All internal registers are strobed on the rising edge of PXCK. LDV 78 59 TTL Pixel Data Load Clock. On each rising edge of LDV, data on PD23-0 are latched into the input preload register, for transfer into the input demultiplexer on the next rising edge of PCK. Frame Buffer Interface PD23-0 52-63, 66-77 26, 27, 31-40, 43-51, 56-58 TTL Pixel Data Inputs. In YCBCR, GBR, RGB, and color-indexed mode, pixel data enter the TMC22x91 on PD23-0. The specific format is found in Figures 1a and 1b. LDV is the clock that controls the loading of pixel data. VHSYNC 12 80 TTL Horizontal Sync I/O. In Master and Genlock modes, the TMC22x91 outputs horizontal sync on this pin. In Slave modes, the TMC22x91 accepts and locks to horizontal sync input on this pin (with vertical sync on VVSYNC). VHSYNC and VVSYNC must be coincident since they are clocked into the TMC22x91 on the same rising edge of PXCK. VVSYNC 13 81 TTL Vertical Sync I/O. In separate V and H sync Master and Genlock modes, the TMC22x91 outputs vertical block sync (VVSYNC LOW for the 2.5 (PAL) or 3 (NTSC) lines on which vertical sync pulses occur). In composite sync (H and V sync on same signal) Master and Genlock modes, the TMC22x91 outputs horizontal sync, vertical sync, and equalization over this pin. In Slave mode, the TMC22x91 accepts and locks to vertical sync input on this pin (with horizontal sync on VHSYNC). VHSYNC and VVSYNC must be coincident such that they are clocked into the TMC22x91 on the same rising edge of PXCK. PDC 11 77 TTL Pixel Data Control. In Master mode, the TMC22x91 forces PDC HIGH when and only when it wants active video from the frame buffer. During blanking (syncs, equalization, burst, and porches), it forces PDC LOW, signaling that it will ignore any data presented over PD23-0. When PDC is used as an input, forcing it HIGH allows the TMC22x91 to receive PD during the active video state. KEY 4 70 TTL Hardware Key Input. When the HKEN control bit is set HIGH and hardware key pin, KEY, is HIGH, video data entering on CVBS7-0 are routed to the COMPOSITE output. This control signal is pipelined so the pixel that is presented to the PD port when the KEY signal is invoked is at the midpoint of the soft key transition. When HKEN is LOW, KEY is ignored. Like PD data, KEY is clocked into the TMC22x91 on the rising edge of LDV. |
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