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TMC2246AG1C1 Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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TMC2246AG1C1 Datasheet(HTML) 10 Page - Fairchild Semiconductor |
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10 / 18 page  PRODUCT SPECIFICATION TMC2246A 10 REV. 1.0.3 9/11/00 Application Notes Typical Operation The versatile input clock enables and unrestricted data and coefficient inputs provided on the TMC2246A allow consid- erable flexibility in numerous image and signal processing architectures. Table 2 shows a typical sequence of operations which clari- fies the inherent latencies of the device and illustrates fixed coefficient storage, product accumulation, and device recon- figuration prior to beginning a new accumulation. This assumes that the device is set to fractional two’s complement mode (FSEL = LOW) with OCEN = LOW, OEN = LOW, and the input registers configured to hold coefficients only (ENSEL = LOW). X= “don’t care.” Using the TMC2246A for Pixel Interpolation As a companion product to the TMC2301 Image Resampling Sequencer, the TMC2246A offers an excellent tool for per- forming high-speed pixel interpolation and image filtering. Any pixel resampling operation with multiple-pixel kernels must utilize some parallel-processing technique, such as memory banding, to maintain high-speed image throughput rates. Memory banding utilizes adders to generate parallel offset addresses, allowing the user to access multiple pixel locations simultaneously. Using such techniques, one TMC2246A can perform bilinear interpolation (four-pixel kernel) with no loss in system performance. Larger kernels can be realized in similar systems with addi- tional TMC2246As. Figure 5 illustrates a basic pixel interpo- lation application. Timing Diagram CLK D1-49-0 CONTROLS1 S15-0 2 DA DB 5 4 3 2 1 SA 1/fCLK tS tH tPWH tDO tHO tPWKL 6 C1-410-0 CA CB Notes: 1. Except OEN. 2. Assumes OEN = LOW. |
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