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APL158125KAC-TRG Datasheet(PDF) 11 Page - Anpec Electronics Coropration |
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APL158125KAC-TRG Datasheet(HTML) 11 Page - Anpec Electronics Coropration |
11 / 20 page Copyright © ANPEC Electronics Corp. Rev. B.8 - Jan., 2012 APL1581 www.anpec.com.tw 11 Figure 3. Recommended SOP-8P Layout Layout and Thermal Consideration (Cont.) Application Information (Cont.) 1 2 3 4 8 7 6 5 Top layer VOUT plane for Heat Dissipation (Larger area is better) COUT CIN Soldering area (140mil x 110mil) for bottom pad Vias Vias CCNTL Load |
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