7

ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY]

8285ES–AVR–02/2013

externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port C also serves the functions of special features of the Atmel

2.3.6

Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the

2.3.7

Port E (PE7:PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the

2.3.8

Port F (PF7:PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal

pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both

high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not

running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be

activated even if a reset occurs.

2.3.9

Port G (PG5:PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port G also serves the functions of various special features of the

2.3.10

Port H (PH7:PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3250A/3250PA/6450A/6450P as listed