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TMC2249AKEC1 Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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TMC2249AKEC1 Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 18 page PRODUCT SPECIFICATION TMC2249A 10 REV. 1.0.2 7/6/00 Application Notes The TMC2249A is a flexible signal and image processing building block with numerous user-selectable functions which expand its usefulness. Table 2 clarifies the operation of the device, demonstrating the various feature available to the user and the timing delays incurred. Table 2. TMC2249A Operation Sequence CASEN = 0, H=HIGH, L=LOW, “ms” indicates most significant output word (bits 23-8), “ls” indicates least significant word (bits 15-0). The appropriate enables for the indicated data are assumed, otherwise ‘-’ indicates that port not enabled. Note that the output data summations including A(8)-D(8) is lost, since the output on cycle 13 is swapped to the LSW of S(12) on cycle 8. In general, RND may be left high unless the ls output is to be used, as on line 8 above. CLK ADEL A 11-0 BDEL B 11-0 CDEL C 11-0 DDEL D 11-0 NEG1 NEG2 CAS15-0 FT ACC RND SWAP S15-0 1 0 A(1) 0 B(1) 0 C(1) 0 D(1) L L 0 L L H H — 2 0 A(2) 0 B(2) 0 C(2) 0 D(2) L H 0 L L H H — 3 0 A(3) 0 B(3) 0 C(3) 0 D(3) H L 0 L L L H — 4 0 A(4) 0 B(4) 0 C(4) 0 D(4) L L CAS(4) L L L H — 5 0 A(5) 0 B(5) 0 C(5) 0 D(5) L L 0 L L L H — 6 0 A(6) 0 B(6) 0 C(6) 0 D(6) L L 0 L L H H (A(1) × B(1)+C(1) × D(1)+27)ms 7 0 A(7) 0 B(7) 0 C(7) 0 D(7) L L 0 L H X H (A(2) × B(2)-C(2) × D(2)+27)ms 8 0 A(8) 0 B(8) 0 C(8) 0 D(8) L L CAS(8) H L L L (-A(3) × B(3)+C(3) × D(3))ms 9 0 A(9) 0 B(9) 0 C(9) 0 D(9) L L 0 L L H H (A(4) × B(4)+C(4) × D(4)+CAS(4))ms 10 (A(5) × B(5)+C(5) × D(5)+CAS(8))ms 11 (A(6) × B(6)+C(6) × D(6)+27)ms 12 (A(7) × B(7)+C(7) × D(7)+S(11))ms 13 (S(12)) ls 14 (A(9) × B(8)+C(7) × D(6)+27)ms Digital Filtering The input structure of the TMC2249A demonstrates great versatility when all four multiplier inputs and the program- mable delay registers are utilized. Table 3 and Table 4 illlustrate how a direct-form symmetric FIR filter of up to 32 taps can be implemented. By utilizing the four input delay registers as pipelined storage banks, the user can store up to 32 coefficient-data word pairs, split into alternate "even" and "odd" halves. Two taps of the filter are calculated on each clock, and the user then increments/decre- ments the delay words (ADEL-DDEL). The sums of prod- ucts are successively added to the global sum in the internal accumulator. Table 3. FIR Filtering with the TMC2249A—Initial Data Loading Even Data Odd Data Coefficient Storage Register Position (Hex) A C B D 0 x(31) x(30) h(0) h(1) 1 x(29) x(28) h(2) h(3) 2 x(27) x(26) h(4) h(5) 3 x(25) x(24) h(6) h(7) 4 x(23) x(22) h(8) h(9) 5 x(21) x(20) h(10) h(11) 6 x(19) x(18) h(12) h(13) 7 x(17) x(16) h(14) h(15) 8 x(15) x(14) h(15) h(14) 9 x(13) x(12) h(13) h(12) A x(11) x(10) h(11) h(10) B x(9) x(8) h(9) h(8) C x(7) x(6) h(7) h(6) D x(5) x(4) h(5) h(4) E x(3) x(2) h(3) h(2) F x(1) x(0) h(1) h(0) |
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