 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
APW7311 Datasheet(PDF) 10 Page - Anpec Electronics Coropration |
|
||||||||||||||||||||||||||||||
APW7311 Datasheet(HTML) 10 Page - Anpec Electronics Coropration |
|
|
10 / 16 page  Copyright © ANPEC Electronics Corp. Rev. P.1 - Jan., 2013 APW7311 www.anpec.com.tw 10 Application Information (Cont.) Thermal Consideration Layout Consideration In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedance should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separating and finally combined using the ground plane construction or single point grounding. Figure 3 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout: 1. Begin the layout by placing the power components first. Orient the power circuitry to achieve a clean power flow path. If possible, make all the connections on one side of the PCB with wide, copper filled areas. 2. In Figure 3, the loops with same color bold lines con- duct high slew rate current. These interconnecting im- pedances should be minimized by using wide and short printed circuit traces. 3. Keep the sensitive small signal nodes (FB, COMP) away from switching nodes (LX or others) on the PCB and it should be placed near the IC as close as possible. Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid switching noise. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace. The APW7311 maximum power dissipation depends on the thermal resistance and temperature difference be- tween the die junction and ambient air. The power dissi- pation P D across the device is: P D = (TJ - TA) / θJA where (T J-TA) is the temperature difference between the junction and ambient air. θ JA is the thermal resistance between Junction and ambient air. For normal operation, do not exceed the maximum junc- tion temperature rating of T J = 125 oC. The calculated power dissipation should less than: P D = (125-25)/75=1.33(W) --- (SOP-8P) 4. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. Use a wide power ground plane to connect the C1, C2, and Schottky diode to provide a low impedance path between the components for large and high slew rate current. Figure 2. Current Path Diagram Figure 3. Recommended Layout Diagram LX EN VIN GND COMP U1 APW7301 FB L1 C2 Load VOUT BS R1 R2 Feedback Divider C5 R3 Compensation Network VIN C3 C1 + + - - SOP-8 APW7301 L1 C2 VLX VIN VOUT Ground Input Capacitor C1 should be near the IC as close as possible Sensitive node (FB, COMP) should be away from switching node(LX) and it should be placed near the IC with short trace Power path should be short and wide Numerous vias connected from the thermal pad to the solderside ground plane(s) should be used to enhance heat dissipation 0 0.5 1 1.5 2 2.5 0 25 50 75 100 125 Ambient Temperature, TA( oC) SOP-8P |
Similar Part No. - APW7311 |
|
Similar Description - APW7311 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
