IP4251_52_53_54-TTL

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Product data sheet

Rev. 2 — 5 May 2011

9 of 18

NXP Semiconductors

IP4251/52/53/54-TTL

Integrated 4-, 6- and 8-channel passive filter network

6.2 Selection

The selection of one of the filter devices has to be performed depending on the maximum

clock frequency, driver strength, capacitive load of the sink, and also the maximum

applicable rise and fall times.

6.2.1 SDHC and MMC memory interface

The Secure Digital High Capacity (SDHC) memory card interface standard specification

and the Multi Media Card (MMC) (JESD 84A43) standard specification recommend a rise

and fall time of 25 % to 62.5 % (62.5 % to 25 % respectively) of 3 ns or less for the input

signal of the receiving interface side.

Assuming a typical capacitance of about 20 pF for the SDHC memory card itself, and

approximately 4 pF to 7 pF for the Printed-Circuit Board (PCB) and the card holder,

matching selection to filter and protect all relevant interface pins such as CLK, CMD, and

DAT0 to DAT3/CD. Please refer to Figure 7 for a general example of the implementation

of the device in an SDHC card interface.

In case additional channels such as write-protect or a mechanical card-detection switch