AK4110 datasheet(5/31 Pages) AKM

Part #	AK4110

Description	High Feature 96kHz 24bit DIR

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Manufacturer	AKM [Asahi Kasei Microsystems]

Direct Link	http://www.akm.com

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ASAHI KASEI

[AK4112A]

MS0020-E-00

2000/3

- 5 -

PIN/FUNCTION

No.

Pin Name

I/O

Function

1

DVDD

-

Digital Power Supply Pin, 3.3V

2

DVSS

-

Digital Ground Pin

3

TVDD

-

Input Buffer Power Supply Pin, 3.3V or 5V

V

O

Validity Flag Output Pin in Parallel Mode

4

TX

O

Transmit channel (through data) Output Pin in Serial Mode

5XTI

I

X'tal Input Pin

6

XTO

O

X'tal Output Pin

7PDN

I

Power-Down Mode Pin

When “L”, the AK4112A is powered-down and reset.

8R

-

External Resistor Pin

18k

W +/-1% resistor to AVSS externally.

9

AVDD

-

Analog Power Supply Pin

10

AVSS

-

Analog Ground Pin

11

RX1

I

Receiver Channel 1

This channel is selected in Parallel Mode or default of Serial Mode.

DIF0

I

Audio Data Interface Format 0 Pin in Parallel Mode

12

RX2

I

Receiver Channel 2 in Serial Mode

DIF1

I

Audio Data Interface Format 1 Pin in Parallel Mode

13

RX3

I

Receiver Channel 3 in Serial Mode

DIF2

I

Audio Data Interface Format 2 Pin in Parallel Mode

14

RX4

I

Receiver Channel 4 in Serial Mode

15

AUTO

O

Non-PCM Detect Pin

“L”: No detect, “H” : Detect

16

P/S

I

Parallel/Serial Select Pin

“L”: Serial Mode, “H”: Parallel Mode

17

FS96

O

96kHz Sampling Detect Pin

(RX Mode)

“H” : fs=88.2kHz or more, “L” fs=54kHz or less.

(X’tal Mode)

“H” : XFS96=1, “L” : XFS96=0.

18

ERF

O

Unlock & Parity Error Output Pin

“L”: No Error, “H”: Error

19

LRCK

I/O

Output Channel Clock Pin

20

SDTO

O

Audio Serial Data Output Pin

21

BICK

I/O

Audio Serial Data Clock Pin

22

DAUX

I

Auxiliary Audio Data Input Pin

23

MCK02

O

Master Clock #2 Output Pin

24

MCK01

O

Master Clock #1 Output Pin

OCKS0

I

Output Clock Select 0 Pin in Parallel Mode

25

CSN

I

Chip Select Pin in Serial Mode

OCKS1

I

Output Clock Select 1 Pin in Parallel Mode

26

CCLK

I

Control Data Clock Pin in Serial Mode

CM1

I

Master Clock Operation Mode Pin0 in Parallel Mode

27

CDTI

I

Control Data Input Pin in Serial Mode

CM0

I

Master Clock Operation Mode Pin1 in Parallel Mode

28

CDTO

O

Control Data Output Pin in Serial Mode

Note 1: All input pins except internal pull-down pins should not be left floating.

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