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AK4351VT Datasheet(PDF) 10 Page - Asahi Kasei Microsystems |
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AK4351VT Datasheet(HTML) 10 Page - Asahi Kasei Microsystems |
10 / 14 page ASAHI KASEI [AK4351] M0022-E-04 1999/12 - 10 - n Power-down The AK4351 is placed in the power-down mode by bringing PD pin “L” and the anlog outputs are floating(Hi-Z). Figure 4 shows an example of the system timing at the power-down and power-up. Normal Operation Internal State PD Power-down Normal Operation GD GD “0”data D/A Out (Analog) D/A In (Digital) Clock In MCLK,LRCK,BICK (1) (2) (4) External Mute (5) (1) (3) (3) Mute On Figure 4. Power-down/up sequence example Notes: (1) Analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi-Z) at the power-down mode. (3) Click noise occures at the edges(“ ¯”) of the falling edge of PD signal. (4) When the external clocks(MCLK,BICK,LRCK) are stopped, the AK4351 should be in the power-down mode. (5) Please mute the analog output externally if the click noise(3) influences system application. The timing example is shown in this figure. n System Reset The AK4351 should be reset once by bringing PD = ”L” upon power-up. The AK4351 is powered up and the internal timing starts clocking by LRCK “ ” after exiting reset and power down state by MCLK. The AK4351 is in power-down mode until MCLK and LRCK are input. |
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