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AD9559PCBZ Datasheet(PDF) 3 Page - Analog Devices

Part # AD9559PCBZ
Description  Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9559PCBZ Datasheet(HTML) 3 Page - Analog Devices

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Data Sheet
AD9559
Rev. 0 | Page 3 of 120
IRQ Mask (Register 0x010A to Register 0x112) .....................74
System Clock (Register 0x0200 to Register 0x0207) ..............76
Reference Input A (Register 0x0300 to Register 0x031A) .....77
Reference Input B (Register 0x0320 to Register 0x033A)......78
Reference Input C (Register 0x0340 to Register 0x035A) .....79
Reference Input D (Register 0x0360 to Register 0x037A).....81
DPLL_0 Controls (Register 0x0400 to Register 0x0415).......82
APLL_0 Configuration (Register 0x0420 to
Register 0x0423)..........................................................................84
PLL_0 Output Sync and Clock Distribution
(Register 0x0424 to Register 0x042E).......................................85
DPLL_0 Settings for Reference Input A (REFA)
(Register 0x0440 to Register 0x044C) ......................................87
DPLL_0 Settings for Reference Input B (REFB)
(Register 0x044D to Register 0x0459)......................................88
DPLL_0 Settings for Reference Input C (REFC)
(Register 0x045A to Register 0x0466)......................................89
DPLL_0 Settings for Reference Input D (REFD)
(Register 0x0467 to Register 0x0473).......................................90
DPLL_1 Controls (Register 0x0500 to Register 0x0515).......91
APLL_1 Configuration (Register 0x0520 to
Register 0x0523)..........................................................................93
PLL_1 Output Sync and Clock Distribution
(Register 0x0524 to Register 0x052E).......................................94
DPLL_1 Settings for Reference Input C (REFC)
(Register 0x0540 to Register 0x054C) ......................................96
DPLL_1 Settings for Reference Input D (REFD)
(Register 0x054D to Register 0x0559)......................................97
DPLL_1 Settings for Reference Input A (REFA)
(Register 0x055A to Register 0x0566)......................................98
DPLL_1 Settings for Reference Input B (REFB)
(Register 0x0567 to Register 0x0573).......................................99
Digital Loop Filter Coefficients (Register 0x0800 to
Register 0x0817)........................................................................100
Common Operational Controls (Register 0x0A00 to
Register 0x0A0E) ......................................................................101
PLL_0 Operational Controls (Register 0x0A20 to
Register 0x0A24).......................................................................104
PLL_1 Operational Controls (Register 0x0A40 to
Register 0x0A44).......................................................................106
Status ReadBack (Register 0x0D00 to Register 0x0D05).....107
IRQ Monitor (Register 0x0D08 to Register 0x0D10) ..........108
PLL_0 Read-Only Status (Register 0x0D20 to
Register 0x0D2A)......................................................................110
PLL_1 Read-Only Status (Register 0x0D40 to
Register 0x0D4A)......................................................................112
EEPROM Control (Register 0x0E00 to Register 0x0E03)...113
EEPROM Storage Sequence (Register 0x0E10 to
Register 0x0E3C).......................................................................113
Outline Dimensions......................................................................120
Ordering Guide .........................................................................120
REVISION HISTORY
7/12—Revision 0: Initial Version


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