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AK4544A Datasheet(PDF) 3 Page - Asahi Kasei Microsystems |
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AK4544A Datasheet(HTML) 3 Page - Asahi Kasei Microsystems |
3 / 35 page [ASAHI KASEI] [AK4544A] <MS0026-E-00> 2000/04 - 3 - Pin/Function No. Signal Name I/O Description 1 DVdd1 - Digital power supply; 3.3V or 5.0V(DVdd1 = DVdd2) 0.1uF + 4.7uF capacitors should be connected to digital ground. 2 XTL_IN (MCLKI) I 24.576MHz(512fs) Crystal is normally connected. If crystal is not connected, external clock can be used. 3 XTL_OUT(open) O 24.576MHz(512fs) Crystal. If external clock is used, this pin should be open. 4 DVss1 - Digital Ground; 0V. This pin should be directly connected to DVss2 on board. 5 SDATA_OUT I Serial 256-bit AC’97 data stream from digital controller 6 BIT_CLK I/O 12.288MHz(256fs) serial data clock Output at Primary codec. Input at Secondary codec. 7 DVss2 - Digital Ground; 0V. This pin should be directly connected to DVss1 on board. 8 SDATA_IN O Serial 256-bit AC’97 data stream to digital controller 9 DVdd2 - Digital power supply; 3.3V or 5.0V(DVdd1 = DVdd2) 0.1uF + 4.7uF capacitors should be connected to digital ground. 10 SYNC I AC’97 Sync Clock, 48kHz(1fs) fixed rate sampling rate 11 RESET# I AC’97 Master Hardware Reset 12 PC_BEEP I PC Speaker beep pass through 13 PHONE I From telephony subsystem speakerphone 14 AUX_L I Aux Left Channel 15 AUX_R I Aux Right Channel 16 VIDEO_L I Video Audio Left Channel 17 VIDEO_R I Video Audio Right Channel 18 CD_L I CD Audio Left Channel 19 CD_GND I CD Audio analog ground CD_GND or analog ground should be connected through capacitor. 20 CD_R I CD Audio Right Channel 21 MIC1 I Desktop Microphone Input 22 MIC2 I Second Microphone Input 23 LINE_IN_L I Line In Left Channel 24 LINE_IN_R I Line In Right Channel 25 AVdd1 - Power supply; 5.0V(AVdd1=AVdd2) 0.1uF + 4.7uF capacitors should be connected to AVss1(analog ground). 26 AVss1 - Analog Ground; 0V 27 Vref O Reference Voltage Output; 0.1 µF +4.7µF capacitors should be connected to Avss1(analog ground). 28 VrefOut O Reference Voltage Output (2.5V,1.25mA) 29 AFILTL O Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor. 30 AFILTR O Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor. 31 VRAD O Vref for ADC ; 0.1 µF capacitor should be connected to analog ground. 32 PLLfilter O Loop filter for PLL is connected; 36k resistor and 33nF capacitor in series and 390pF capacitor. 33 VRDA O Vref for DAC; 0.1 µF capacitor should be connected to analog ground. 34 3Dcap O 3D Enhancement Cap; 27nF capacitor should be connected to analog ground. 35 LINE_OUT_L O Line Out Left Channel 36 LINE_OUT_R O Line Out Right Channel 37 MONO_OUT O To telephony subsystem speakerphone 38 AVdd2 - Power supply; 5.0V(AVdd1=AVdd2) 0.1uF capacitor should be connected to AVss2(analog ground). 39 LNLVL_OUT_L O True Line Level Out Left Channel 40 NC - No Connection 41 LNLVL_OUT_R O True Line Level Out Right Channel 42 AVss2 - Analog Ground 43 TEST2 I Test pin (This pin should be open for normal operation):With internal pull-down. 44 TEST3 I Test pin (This pin should be open for normal operation):With internal pull-down. 45 Codec ID0# I Codec ID configuration(ID select input for multiple codec extension) See Page21. Negative logic input. With internal pull-up. 46 Codec ID1# I Codec ID configuration(ID select input for multiple codec extension) See Page21. Negative logic input. With internal pull-up. |
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