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THS4500CDGKRG4 Datasheet(PDF) 2 Page - Texas Instruments |
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THS4500CDGKRG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 48 page THS4500 THS4501 SLOS350F – APRIL 2002 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. UNIT Supply voltage, VS 16.5 V Input voltage, VI ±VS Output current, IO (2) 150 mA Differential input voltage, VID 4 V Continuous power dissipation See Dissipation Rating Table Maximum junction temperature, TJ (3) +150 °C Maximum junction temperature, continuous operation, long-term reliability, TJ +125 °C C suffix 0 °C to +70°C Operating free-air temperature range, TA (4) I suffix –40°C to +85°C Storage temperature range, Tstg –65°C to +150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds +300 °C HBM 4000 V ESD rating: CDM 1000 V MM 100 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The THS4500/1 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally-enhanced package. (3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process. (4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. DISSIPATION RATINGS TABLE POWER RATING(2) θJC θJA (1) PACKAGE ( °C/W) ( °C/W) TA ≤ +25°C TA = +85°C D (8-pin) 38.3 97.5 1.02 W 410 mW DGN (8-pin) 4.7 58.4 1.71 W 685 mW DGK (8-pin) 54.2 260 385 mW 154 mW (1) This data was taken using the JEDEC standard High-K test PCB. (2) Power rating is determined with a junction temperature of +125 °C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below +125 °C for best performance and long-term reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Dual supply ±5 ±7.5 Supply voltage V Single supply 4.5 5 15 C suffix 0 +70 Operating free- air temperature, TA °C I suffix –40 +85 2 Submit Documentation Feedback Copyright © 2002–2011, Texas Instruments Incorporated Product Folder Link(s): THS4500 THS4501 |
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