TLK1521

500 Mbps to 1.3 Gbps TRANSCEIVER

SLLS591C− OCTOBER 2003 − REVISED JULY 2007

9

POST OFFICE BOX 655303

TERMINAL

DESCRIPTION

TYPE

NAME

DESCRIPTION

TYPE

NO.

RXD0

51

RXD1

50

RXD2

49

RXD3

47

RXD4

46

RXD5

45

RXD6

44

RXD7

42

Output

Receive data bus. These outputs carry 18-bit parallel data output from the transceiver to the protocol

RXD8

40

Output

(High-Z on

Receive data bus. These outputs carry 18-bit parallel data output from the transceiver to the protocol

device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 7.

RXD9

39

(High-Z on

power up)

device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 7.

These pins are tri-stated during power-on reset. These pins are also high impedance when enable = 0

RXD10

37

power up)

These pins are tri-stated during power-on reset. These pins are also high impedance when enable = 0

RXD11

36

RXD12

35

RXD13

34

RXD14

32

RXD15

31

RXD16

30

RXD17

29

RX_CLK

41

Output (low

on power

up)

Recovered clock. Output clock that is synchronized to RXD. RX_CLK is the recovered serial data rate

clock divided by 20. RX_CLK is held low during power-on reset. These pins are also high impedance when

enable = 0

SYNC

25

Input

(w/pulldown)

Fast

synchronization.

When

asserted

high,

the

transmitter

substitutes

the

18-bit

pattern

111111111000000000, so that when the start/stop bits are framed around the data the receiver can

immediately detect the proper deserialization boundary. This is typically used during initialization of the

serial link.

PREEMPH

56

Input

Preemphasis. When asserted, the serial transmit outputs have an extra output swing on the first bit of any

run-length of same value bits. If the run-length of output bits is one, then that bit has a larger output swing.

TEST PIN

ENABLE

24

Input

(w/pullup)

Device enable. When this pin is held low, the device is placed in power down mode. When asserted high

while the device is in power-down mode, the transceiver goes into power-on reset before beginning

normal operation.

LOOPEN

21

Input

(w/pulldown)

Loop enable. When LOOPEN is active high, the internal loop-back path is activated. The transmitted serial

data is directly routed internally to the inputs of the receiver. This provides a self-test capability in

conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a

high-impedance state during the loop-back test. LOOPEN is held low during standard operational state

with external serial outputs and inputs active.

LOCKB

26

Output

Receiver lock. When asserted low, it indicates that the receiver has acquired bit synchronization on the

data stream and has located the start/stop bits, so that the deserialized data presented on the parallel

receive bus is properly received. This pin is high impedance when enable = 0.

TESTEN

27

Input

(w/pulldown)

Test mode enable. This pin should be left unconnected or tied low.

POWER PIN

VDD

1, 9,

23,

38,

48

Supply

Digital logic power. Provides power for all digital circuitry and digital I/O buffers.

VDDA

55,

57

Supply

Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and

transmitter.