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AK6420BH Datasheet(PDF) 5 Page - Asahi Kasei Microsystems |
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AK6420BH Datasheet(HTML) 5 Page - Asahi Kasei Microsystems |
5 / 15 page ASAHI KASEI [AK6420B/40B/80B] DAS03E-00 1999/05 - 5 - Functional Description The AK6420B/40B/80B has 4 instructions such as READ, WRITE, WREN (write enable) and WRDS (write disable). Each instruction is organized by op-code block (8bits), address block (8bits) and data (8bits Õ2). When input level of SK pin is high level and input level of chip select (CS) pin is changed from high level to low level, AK6420B/40B/80B can receive the instructions. When the instructions are executed consecutively, the CS pin should be brought to high level for a minimum of 250ns(Tcs) between consecutive instruction cycle. Instruction Set For 6420B Instruction Op-Code Address Data READ 1 0 1 0 1 0 0 0 A6 A5 A4 A3 A2 A1 A0 0 D15 -D0 WRITE 1 0 1 0 0 1 0 0 A6 A5 A4 A3 A2 A1 A0 0 D15 -D0 WREN 1 0 1 0 0 0 1 1 ÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ WRDS 1 0 1 0 0 0 0 0 ÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ ( WRAL ) 1 0 1 0 1 1 1 1 ÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ D15 -D0 Instruction Set For 6440B Instruction Op-Code Address Data READ 1 0 1 0 1 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0 WRITE 1 0 1 0 0 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0 WREN 1 0 1 0 0 0 1 1 ÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ WRDS 1 0 1 0 0 0 0 0 ÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ ( WRAL ) 1 0 1 0 1 1 1 1 ÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ D15 -D0 Instruction Set For 6480B Instruction Op-Code Address Data READ 1 0 1 0 1 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0 WRITE 1 0 1 0 0 1 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 -D0 WREN 1 0 1 0 0 0 1 1 ÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ WRDS 1 0 1 0 0 0 0 0 ÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ ( WRAL ) 1 0 1 0 1 1 1 1 ÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ D15 -D0 Õ:don't care (Note) The WRAL instruction is used for factory function test only. User can't use this instruction . |
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