ASAHI KASEI

[AK93C41A/51A]

DAM05E-01

1999/12

- 5 -

Write

The write instruction is followed by 16 bits of data to be written into the specified address.

The self-timed programming cycle is initiated on the rising edge of the SK clock as the last data bit (D0) is

clocked in. The DO indicates the Busy/Ready status of the chip after the self-timed programming cycle is

initiated.

The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO output goes

into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is

given to the part.

DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the register at the

address specified in the instruction has been written with the new data pattern contained in the instruction and

the part is ready for a next instruction.

WRITE (AK93C41A)

WRITE (AK93C51A)