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AKD4393 Datasheet(PDF) 3 Page - Asahi Kasei Microsystems |
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AKD4393 Datasheet(HTML) 3 Page - Asahi Kasei Microsystems |
3 / 21 page ASAHI KASEI [AKD4393] <KM058804> 3 2000/5 <The evaluation modes and corresponding jumper pins setting 1. Evaluation Modes •Applicable Evaluation Mode (1) DIR(Optical Link) (2) Ideal sine wave generated by ROM data (3) Using AD converted data (4)All interface signals including master clock are fed externally. (1) DIR(Optical Link) (default) PORT2 is used for the evaluation using such as CD test disk. The DIR generates MCLK, BICK and LRCK SDATAfrom the received data through optical connector(PORT2: TORX176). Fig.3 Jumper set-up (DIR) (2) Ideal sine wave generated by ROM data Digital signal generated by AKD43XX are used. PORT1 is used for the interface with AKD43XX. Master clock is sent from AKD4393 to AKD43XX then LRCK, BICK and SDATA are sent from AKD43XX to AKD4393. JP7 SD JP6 LR XTL/E X T DIR JP5 BI XTL/E X T DIR CLK JP9 DIR EXT XTL JP8 CKDIV 1 2X 1X JP4 BCP INV THR JP2 C S 8414 VDD GND JP1 JP14 CKDIV 2 1/2X 1X XTL Fig.4 Jumper set-up (ROM data) JP7 SD JP6 LR XTL/EXT DIR JP5 BI XTL/EXT DIR CLK JP9 DIR EXT XTL JP4 JP8 CKDIV1 2X 1X BCP INV THR BCP INV THR (others) (MSB justified) JP2 CS8414 VDD GND JP1 JP14 CKDIV2 1/2X 1X XTL |
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