CAT34TS04VP2GT4A datasheet(6/18 Pages) ONSEMI

Part #	CAT34TS04VP2GT4A

Description	Digital Output Temperature Sensor with On-board SPD EEPROM

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Manufacturer	ONSEMI [ON Semiconductor]

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CAT34TS04

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SPD EEPROM Bank Selection

Upon power−up, the address pointers for both the

Temperature Sensor (TS) and on−board EEPROM are

initialized to 00h. The TS address pointer will thus point to

the Capability Register and the EEPROM address pointer

will point to the first location in the lower 2−Kb bank (SPD

page 0).

Only one SPD page is visible (active) at any given time.

The lower SPD page is automatically selected at power−up.

The upper SPD page can be activated (and the lower one

implicitly de−activated) by executing the SPA1 utility

command. The SPA0 utility command can then be used to

re−activate the lower SPD page without powering down.

The identity of the active SPD page can be retrieved with the

RPA command.

SPD page selection related command details are

presented in Table 9c, Table 9d, Figure 13 and Figure 14.

Write Operations

EEPROM Byte and TS Register Write

To write data to a TS register, or to the on−board

EEPROM, the Master creates a START condition on the bus,

and then sends out the appropriate Slave address (with the

R/W bit set to ‘0’), followed by a starting data byte address

or TS register address, followed by data. The matching

Slave will acknowledge the Slave address, EEPROM byte

address or TS register address and the data byte(s), one for

EEPROM data (Figure 6) and two for TS register data

(Figure 7). The Master then ends the session by creating a

STOP condition on the bus. The STOP completes the

(volatile) TS register update or starts the internal Write cycle

for the (non−volatile) EEPROM data (Figure 8).

EEPROM Page Write

Each of the two 2−Kb banks is organized as 16 pages of

16 bytes each (not to be confused with the SPD page, which

refers to the entire 2−Kb bank). One of the 16 memory pages

is selected by the 4 most significant bits of the byte address,

while the 4 least significant bits point to the byte position

within the page. Up to 16 bytes can be written in one Write

cycle (Figure 9).

During data load, the internal byte position pointer is

automatically incremented after each data byte is loaded. If

the Master transmits more than 16 data bytes, then earlier

data will be replaced by later data in a ‘wrap−around’

fashion within the 16−byte wide data buffer. The internal

Write cycle then starts following the STOP.

Acknowledge Polling

Acknowledge polling can be used to determine if the

CAT34TS04 is busy writing to EEPROM, or is ready to

accept commands. Polling is executed by interrogating the

device with a ‘Selective Read’ command (see READ

OPERATIONS). The CAT34TS04 will not acknowledge

the Slave address as long as internal EEPROM Write is in

progress.

Delivery State

The CAT34TS04 is shipped ‘unprotected’, i.e. none of the

Software Write Protection (SWP) flags is set. The entire

memory is erased, i.e. all bytes are 0xFF.

Read Operations

Immediate Read

A CAT34TS04 presented with a Slave address containing

a ‘1’ in the R/W position will acknowledge the Slave address

and will then start transmitting SPD data or respectively TS

register data from the current address pointer location. The

Master stops this transmission by responding with NoACK,

followed by a STOP (Figures 10a, 10b).

Selective Read

The Read operation can be started from a specific address,

by preceding the Immediate Read sequence with a ‘data less’

Write sequence. The Master sends out a START, Slave

address and byte or register address, but rather than

following up with data (as in a Write operation), the Master

then issues another START and continuous with an

Immediate Read sequence (Figures 11a, 11b).

Sequential EEPROM Read

EEPROM data can be read out indefinitely, as long as the

Master responds with ACK (Figure 12). The internal address

pointer is automatically incremented after every data byte

sent to the bus. If the end of the active 2−Kb bank is reached

during continuous Read, then the address count

‘wraps−around’ to the beginning of the active 2−Kb bank,

etc. Sequential Read works with either Immediate Read or

Selective Read, the only difference being that in the latter

case the starting address is intentionally updated.

Figure 6. EEPROM Byte Write

BYTE

ADDRESS

SLAVE

SPD

ADDRESS

S

A

C

K

A

C

K

DATA

A

C

K

S

T

O

P

BUS ACTIVITY:

MASTER

SLAVE

SDA LINE

S

T

A

R

T

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CAT34TS04VP2GT4A Datasheet(PDF) 6 Page - ON Semiconductor

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