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CAT34TS04HU4GT4A Datasheet(PDF) 11 Page - ON Semiconductor

Part # CAT34TS04HU4GT4A
Description  Digital Output Temperature Sensor with On-board SPD EEPROM
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT34TS04HU4GT4A Datasheet(HTML) 11 Page - ON Semiconductor

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CAT34TS04
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Table 10. THE TS REGISTERS
Register Address
Register Name
Power−On Default
Read/Write
0x00
Capability Register
0x007F
Read
0x01
Configuration Register
0x0000
Read/Write
0x02
High Limit Register
0x0000
Read/Write
0x03
Low Limit Register
0x0000
Read/Write
0x04
Critical Limit Register
0x0000
Read/Write
0x05
Temperature Data Register
Undefined
Read
0x06
Manufacturer ID Register
0x1B09
Read
0x07
Device ID/Revision Register
0x2200
Read
Table 11. CAPABILITY REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
RFU
(Note 16)
RFU
RFU
RFU
RFU
RFU
RFU
RFU
B7
B6
B5
B4
B3
B2
B1
B0
EVSD
TMOUT
VHV
TRES [1:0]
RANGE
ACC
EVENT
16.RFU stands for Reserved for Future Use
Bit
Description
B15:B8
Reserved for future use; can not be written; should be ignored; will read as 0
B7 (Note 17)
0:
Configuration Register bit 4 is frozen upon Configuration Register bit 8 being set
(i.e. a TS shut−down freezes the EVENT output)
1:
Configuration Register bit 4 is cleared upon Configuration Register bit 8 being set
(i.e. a TS shut−down de−asserts the EVENT output)
B6
0:
Not used
1:
The TS implements SMBus time−out within the range 25 to 35 ms
B5
0:
Not used
1:
Defined for compatibility with CAT34TS02 device (VHV is supported)
B4:B3
00: LSB = 0.50°C (9 bit resolution)
01: LSB = 0.25°C (10 bit)
10: LSB = 0.125°C (11 bit)
11: LSB = 0.0625°C (12 bit)
B2
0:
Not used
1:
The temperature monitor can read temperatures below 0°C and sets the sign bit appropriately
B1
0:
Not used
1:
The temperature monitor has ±1°C accuracy over the active range (75°C to 95°C) and ±2°C
accuracy over the monitoring range (40°C to 125°C)
B0
0:
Not used
1:
The device supports interrupt capabilities
17.Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a “1” to Configuration Register
bit 5 (EVENT output can be de−asserted during TS shut−down periods)


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