ADS61JB46 datasheet(9/48 Pages) TI1

Part #	ADS61JB46

Description	14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter with JESD204A Output Interface

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Manufacturer	TI1 [Texas Instruments]

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Input

Clock

Input

Signal

Sample

N

N+1

N+2

N+3

N+4

CLKM

CLKP

CML Output

Data Lane 1

SYNC~ Input

(SYNC~P)

(SYNC~M)

-

N-12

N-11

N+5

N+6

N+7

N+8

N+9

t

SYNCZ-H

t

SYNCZ-SU

SYNC~ De-Active

Latency = 8 Clock Cycles

t

SYNCZ-PDI

K28.5

N-12

K28.5

N-11

K28.5

Internal Clock

for Latching SYNC

(CLK_INT)

t

CLK-INT

CML Output

Data Lane 2

ADS61JB46

www.ti.com

SBAS611B – SEPTEMBER 2013 – REVISED OCTOBER 2013

Figure 6. SYNC~ De-Active Timing Diagram

Table 3. SYNC~ Rising Edge Timing at 160 MSPS

PARAMETER

DESCRIPTION

TYP

UNIT

Delay from input clock rising edge to the internal clock (CLK_INT)

10.5

ns

tCLK-INT

rising edge used to latch the SYNC~ rising edge

tSYNCZ-SU

SYNC~ active edge setup time

Minimum delay required from SYNC~ rising edge to CLK_INT rising

2

ns

edge

tSYNCZ-H

SYNC~ active edge hold time

Minimum delay required from CLK_INT rising edge to SYNC~ rising

2

ns

edge

SYNC~ de-active latency

Number of clocks for normal data to appear at the output after a

8

Clocks

SYNC~ de-activate request

tSYNCZ-PDI

SYNC~ de-active data

Similar to data propagation delay

15.3

ns

propagation delay

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