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BQ500212ARGZR Datasheet(PDF) 3 Page - Texas Instruments

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Part # BQ500212ARGZR
Description  Low System Cost, Wireless Power Controller for WPC TX A5 or A11
Download  28 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

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bq500212A
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SLUSBD6B – JULY 2013 – REVISED NOVEMBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP MAX
UNIT
V
Supply voltage during operation, V33D, V33A
3.0
3.3
3.6
V
TA
Operating free-air temperature range
–40
110
°C
TJ
Junction temperature
110
THERMAL INFORMATION
bq500212A
THERMAL METRIC(1)
RGZ
UNITS
48 PINS
θJA
Junction-to-ambient thermal resistance(2)
28.4
θJCtop
Junction-to-case (top) thermal resistance(3)
14.2
θJB
Junction-to-board thermal resistance(4)
5.4
°C/W
ψJT
Junction-to-top characterization parameter(5)
0.2
ψJB
Junction-to-board characterization parameter(6)
5.3
θJCbot
Junction-to-case (bottom) thermal resistance(7)
1.4
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3)
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4)
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5)
The junction-to-top characterization parameter,
ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6)
The junction-to-board characterization parameter,
ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7)
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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