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C1005X5R1A225 Datasheet(PDF) 4 Page - Texas Instruments |
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C1005X5R1A225 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 36 page LM3697 SNOSCS2A – NOVEMBER 2013 – REVISED DECEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (1) (2) Limits in standard type face are for TA = +25°C and those in boldface type apply over the full operating ambient temperature range ( −40°C ≤ TA ≤ +85°C). Unless otherwise specified VIN = 3.6V. Symbol Parameter Conditions Min Typ Max Units ISHDN Shutdown Current 2.7V ≤ VIN ≤ 5.5V, HWEN = GND 1 3.0 µA Full-Scale Current = 20.2 mA ILED_MIN Minimum LED Current 6.0 µA Exponential Mapping Thermal Shutdown 140 TSD °C Hysteresis 15 Boost Converter Output Current Regulation 2.7V ≤ VIN ≤ 5.5V, Full-Scale Current = 20.2 IHVLED(1/2/3) 18.38 20.2 22.02 mA (HVLED1, HVLED2, HVLED3) mA, Brightness Code = 0xFF Control Bank A, Exponential Mapping, −2.5 2.5 % Autoheadroom Off, PWM Off, ILED = 20.2 mA HVLED1 to HVLED2 or HVLED3 IMATCH_HV 2.7V ≤ VIN ≤ 5.5V Matching (3) Control Bank A, Exponential Mapping, -8.5 8.5 % Autoheadroom Off, PWM Off, ILED = 500 µA Regulated Current Sink VREG_CS Auto-headroom off 400 mV Headroom Voltage Minimum Current Sink Headroom ILED = 95% of nominal, Full-Scale Current = VHR_HV 190 275 mV Voltage for HVLED Current Sinks 20.2 mA RDSON NMOS Switch On Resistance ISW = 500 mA 0.3 Ω ICL_BOOST NMOS Switch Current Limit VIN = 3.6V 880 1000 1120 mA ON Threshold, 2.7V ≤ VIN ≤ 5.5V 38.75 40 41.1 OVP select bits = 11 VOVP Output Over-Voltage Protection V Hysteresis 1 Boost Frequency Select 450 500 550 Bit = 0 fSW Switching Frequency 2.7V ≤ VIN ≤ 5.5V kHz Boost Frequency Select 900 1000 1100 Bit = 1 DMAX Maximum Duty Cycle 94 % HWEN Input Logic Low 0 0.4 VHWEN Logic Thresholds V Logic High 1.2 VIN PWM Input VPWM_L Input Logic Low 2.7V ≤ VIN ≤ 5.5V 0 400 mV VPWM_H Input Logic High 2.7V ≤ VIN ≤ 5.5V 1.31 VIN V tPWM Minimum PWM input pulse 2.7V ≤ VIN ≤ 5.5V PWM Zero Detect enabled 0.75 µs I2C-Compatible Voltage Specifications (SCL, SDA) VIL Input Logic Low 2.7V ≤ VIN ≤ 5.5V 0 400 mV VIH Input Logic High 2.7V ≤ VIN ≤ 5.5V 1.29 VIN V VOL Output Logic Low (SDA) ILOAD = 3 mA 400 mV I2C-Compatible Timing Specifications (SCL, SDA) (4), (see Figure 2) t1 SCL (Clock Period) 2.5 µs t2 Data In Setup Time to SCL High 100 ns t3 Data Out Stable After SCL Low 0 ns (1) All voltages are with respect to the potential at the GND pin. (2) Min and Max limits are verified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: VIN = 3.6V and TA = +25°C. (3) LED current sink matching in the high-voltage current sinks (HVLED1 through HVLED3) is given as the maximum matching value between any two current sinks, where the matching between any two high voltage current sinks (X and Y) is given as (IHVLEDX ( or IHVLEDY) - IAVE(X-Y))/(IAVE(X-Y)) x 100. In this test all three HVLED current sinks are assigned to Bank A. (4) SCL and SDA must be glitch-free in order for proper brightness control to be realized. 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3697 |
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