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MSP430TCH5EPW Datasheet(PDF) 8 Page - Texas Instruments |
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MSP430TCH5EPW Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 67 page  MSP430TCH5E SLAS895 – DECEMBER 2013 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NO. I/O DESCRIPTION NAME PW28 RHB32 RST/ Reset NMI/ 24 23 I Nonmaskable interrupt input SBWTDIO Spy-Bi-Wire test data input/output during programming and test TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. 25 24 I SBWTCK Spy-Bi-Wire test clock input during programming and test AVCC NA 29 NA Analog supply voltage DVCC 1 30 NA Digital supply voltage DVSS 28 27, 28 NA Ground reference NC NA 8, 32 NA Not connected QFN Pad NA Pad NA QFN package pad. Connection to VSS is recommended. Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: MSP430TCH5E |
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