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SN65LVDS822RGZR Datasheet(PDF) 9 Page - Texas Instruments |
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SN65LVDS822RGZR Datasheet(HTML) 9 Page - Texas Instruments |
9 / 27 page SN65LVDS822 www.ti.com SLLSEE8A – SEPTEMBER 2013 – REVISED OCTOBER 2013 POWER SUPPLY CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS(1) (2) TYP MAX(1) UNIT Grayscale pattern; outputs terminated with 10 pF; SLEW = Low; fCLK = 10 MHz 24.6 mA MODE14 = Low, VDD = 3.3 V, VDDIO = 1.8 V SLEW = Low; fCLK = 10 MHz 25.7 Grayscale pattern; outputs terminated with 10pF; SLEW = Float; fCLK = 20 MHz 30.9 mA MODE14 = Low, VDD = VDDIO = 3.3 V SLEW = High; fCLK = 54 MHz 51.5 Total average supply IDD SLEW = Float; fCLK = 20 MHz 48.2 59 1010 pattern; outputs terminated with 10 pF; current of VDD and VDDIO mA MODE14 = Low, VDD = VDDIO = 3.6 V SLEW = High; fCLK = 54 MHz 101.7 124 fCLK < 500 kHz; 4 7 mA VCM-CLKP/N ≤ 0.80 x VDD LVDS inputs are open; CMOS Standby Mode inputs held static; Outputs VCM-CLKP/N > 0.95 x VDD 75 130 terminated with 10 pF µA Shutdown Mode SHTDN# = Low 4 20 Grayscale pattern; outputs terminated with 10 pF; SLEW = Low; fCLK = 10 MHz 83 MODE14 = Low, VDD = 3.3 V, VDDIO = 1.8 V PD Power Dissipation mW 1010 pattern; outputs terminated with 10 pF; SLEW = High; fCLK = 54 MHz 366 446 MODE14 = Low, VDD = VDDIO = 3.6 V (1) Grayscale and 1010 test patterns are described by Figure 6 to Figure 7 and Table 1 to Table 2. (2) Standby Mode can be entered in two ways: fCLK = zero to 500 kHz, or a high VCM on the LVDS clock. If the LVDS transmitter device disables its clock driver to a high-impedance state, the SN65LVDS822’s integrated RPU will pull VCM high for the lower-power Standby state. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links :SN65LVDS822 |
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