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TLV70030QDCKRQ1 Datasheet(PDF) 4 Page - Texas Instruments |
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TLV70030QDCKRQ1 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 19 page OUT N/C (1) IN GND EN 1 2 3 5 4 OUT N/C (1) IN GND EN 1 2 3 5 4 Thermal Shutdown Current Limit UVLO Bandgap IN EN OUT LOGIC GND TLV700xx-Q1 Series TLV70012A-Q1, TLV70025-Q1, TLV70028-Q1 TLV70030-Q1, TLV70032-Q1, TLV70033-Q1 SLVSA61F – FEBRUARY 2010 – REVISED AUGUST 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS TLV700xx-Q1 DDC TLV700xx-Q1 DCK SOT23-5 PACKAGE SC70-5 PACKAGE (TOP VIEW) (TOP VIEW) PIN DESCRIPTIONS NAME NO. DESCRIPTION Input pin. A small 1- μF ceramic capacitor is recommended from this pin to ground to assure stability and good IN 1 transient performance. See Input and Output Capacitor Requirements in the Application Information section for more details. GND 2 Ground pin Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown EN 3 mode and reduces operating current to 1 μA, nominal. NC 4 No connection. This pin can be tied to ground to improve thermal dissipation. Regulated output voltage pin. A small 1- μF ceramic capacitor is needed from this pin to ground to assure stability. OUT 5 See Input and Output Capacitor Requirements in the Application Information section for more details. 4 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70028-Q1 TLV70030-Q1 TLV70032-Q1 TLV70033-Q1 |
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