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3953 Datasheet(PDF) 8 Page - Allegro MicroSystems |
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3953 Datasheet(HTML) 8 Page - Allegro MicroSystems |
8 / 14 page 3953 FULL-BRIDGE PWM MOTOR DRIVER 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8 LOAD CURRENT REGULATION WITH INTERNAL PWM CURRENT-CONTROL CIRCUITRY When the device is operating in slow current-decay mode, there is a limit to the lowest level that the PWM current-control circuitry can regulate load current. The limitation is the minimum duty cycle, which is a function of the user-selected value of tOFF and the minimum on-time pulse tON(min) max that occurs each time the PWM latch is reset. If the motor is not rotating (as in the case of a stepper motor in hold/detent mode, a brush dc motor when stalled, or at startup), the worst case value of current regulation can be approximated by: where tOFF = RT x CT, RLOAD is the series resistance of the load, VBB is the motor supply voltage and t ON(min)max is specified in the electrical characteristics table. When the motor is rotating, the back EMF generated will influence the above relationship. For brush dc motor applications, the current regulation is improved. For stepper motor applications, when the motor is rotating, the effect is more complex. A discussion of this subject is included in the section on stepper motors below. The following procedure can be used to evaluate the worst-case slow current-decay internal PWM load current regulation in the system: Set VREF to 0 volts. With the load connected and the PWM current control operating in slow current-decay mode, use an oscilloscope to measure the time the output is low (sink on) for the output that is chopping. This is the typical minimum on time (tON(min) typ) for the device. The CT then should be increased until the measured value of tON(min) is equal to tON(min) max as specified in the electrical characteristics table. When the new value of CT has been set, the value of RT should be decreased so the value for tOFF = RT x CT (with the artificially increased value of CT) is equal to the nominal design value. The worst-case load- current regulation then can be measured in the system under operating conditions. PWM of the PHASE and ENABLE Inputs. The PHASE and ENABLE inputs can be pulse-width modulated to regulate load current. Typical propagation delays from the PHASE and ENABLE inputs to transitions of the power outputs are specified in the electrical characteris- tics table. If the internal PWM current control is used, the comparator blanking function is active during phase and enable transitions. This eliminates false tripping of the over-current comparator caused by switching transients (see “RC Blanking” above). Enable PWM. With the MODE input low, toggling the ENABLE input turns on and off the selected source and sink drivers. The corresponding pair of flyback and ground-clamp diodes conduct after the drivers are disabled, resulting in fast current decay. When the device is enabled the internal current-control circuitry will be active and can be used to limit the load current in a slow current-decay mode. For applications that PWM the ENABLE input and desire the internal current-limiting circuit to function in the fast decay mode, the ENABLE input signal should be inverted and connected to the MODE input. This prevents the device from being switched into sleep mode when the ENABLE input is low. Phase PWM. Toggling the PHASE terminal selects which sink/source pair is enabled, producing a load current that varies with the duty cycle and remains continuous at all times. This can have added benefits in bidirectional brush dc servo motor applications as the transfer function between the duty cycle on the PHASE input and the average voltage applied to the motor is more linear than in the case of ENABLE PWM control (which produces a discontinuous current at low current levels). For more information see “DC Motor Applications” below. Synchronous Fixed-Frequency PWM. The internal PWM current-control circuitry of multiple A3953S— devices can be synchronized by using the simple circuit shown in figure 3. A 555 IC can be used to generate the reset pulse/blanking signal (t1) for the device and the period of the PWM cycle (t2). The value of t1 should be a minimum of 1.5 ms. When used in this configuration, the RT and CT components should be omitted. The PHASE and ENABLE inputs should not be PWM with this circuit configuration due to the absence of a blanking function synchronous with their transitions. [(VBB – VSAT(source+sink)) x tON(min)max] – (1.05(VSAT(sink) + VF) x tOFF) 1.05 x (tON(min)max + tOFF) x RLOAD IAVE ≈ |
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