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TMP320F28376DPTPQ Datasheet(PDF) 4 Page - Texas Instruments |
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TMP320F28376DPTPQ Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 110 page  16-/12-bit ADC x4 Analog Mux ADC Result Regs Peripheral Frame 1 Global Shared 16x 4Kx16 GS0-GS15 RAMs CPU1 to CPU2 1Kx16 MSG RAM GPIO MUX PUMP OTP/Flash Wrapper CPU1.M0 RAM 1Kx16 CPU1.M1 RAM 1Kx16 CPU2.M0 RAM 1Kx16 CPU2.M1 RAM 1Kx16 IPC FLASH 256Kx16 Secure OTP/Flash Wrapper FLASH 256Kx16 Secure Dual Code Security Module + ECSL Dual Code Security Module + ECSL User OTP 1Kx16 PSWD PSWD Secure Memories shown in Blue User OTP 1Kx16 MEMCPU2 CPU2 to CPU1 1Kx16 MSG RAM MEMCPU1 ADCINCAL0 A5:0 B5:0 C5:2 ADCINCAL1 CPU1 Buses CPU2 Buses SCI- A/B/C/D (16L FIFO) I2C-A/B (16L FIFO) D5:0 Comparator SubSystem (CMPSS) DAC x3 Config C28 CPU-1 FPU VCU-II TMU CPU Timer 0 CPU Timer 1 CPU Timer 2 ePIE (up to 192 interrupts) WD Timer NMI-WDT C28 CPU-2 FPU VCU-II TMU CPU Timer 0 CPU Timer 1 CPU Timer 2 ePIE (up to 192 interrupts) WD Timer NMI-WDT CPU1.CLA1 Data ROM (4Kx16) CPU1.CLA1 to CPU1 128x16 MSG RAM CPU1 to CPU1.CLA1 128x16 MSG RAM CPU1.D0 RAM 2Kx16 CPU1.D1 RAM 2Kx16 Boot-ROM 32Kx16 Non Secure Secure-ROM 32Kx16 Secure CPU1 Local Shared 6x 2Kx16 LS0-LS5 RAMs CPU2 to CPU2.CLA1 128x16 MSG RAM CPU2.CLA1 to CPU2 128x16 MSG RAM CPU2.D0 RAM 2Kx16 CPU2.D1 RAM 2Kx16 CPU2.CLA1 Data ROM (4Kx16) Boot-ROM 32Kx16 Non Secure Secure-ROM 32Kx16 Secure CPU2 Local Shared 2Kx16 LS0-LS5 RAMs CPU1.CLA1 CPU1.DMA CPU2.DMA CPU2.CLA1 Data Bus Bridge Data Bus Bridge ePWM-1/../12 eCAP- 1/../6 eQEP-1/2/3 HRPWM-1/../8 SD-1/../8 CAN- A/B (32-mbox) Data Bus Bridge McBSP- A/B uPP RAM Peripheral Frame 2 SPI- A/B/C (16L FIFO) GPIO Data Bus Bridge Data Bus Bridge USB Ctrl / PHY USB Ctrl / PHY EMIF1 Data Bus Bridge EMIF2 Data Bus Bridge A B C D JTAG AUXCLKIN External Oscillator Watchdog 1/2 Main PLL Aux PLL INTOSC1 INTOSC2 Low-Power Mode Control GPIO Mux TRST TCK TDI TMS TDO TMS320F28377D, TMS320F28376D SPRS880 – DECEMBER 2013 www.ti.com 1.4 Functional Block Diagram Figure 1-1 shows the CPU system and associated peripherals comprising the F2837xD device. Figure 1-1. Functional Block Diagram 4 TMS320F2837xD Dual-Core Delfino MCUs Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320F28377D TMS320F28376D |
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