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TPS7B6701-Q1 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS7B6701-Q1 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 24 page VIN VOUT RESET UVThres VTH(POR) VTH(RST_DLY) tRST_ DEGLITCH tRST_DELAY t <tRST_DEGLITCH tRST_ DEGLITCH VTH(RST_DLY) tRST_ DELAY Internally Set DELAY DELAY d C 1 V t 9.5 µA ´ = TPS7B6701-Q1 TPS7B6733-Q1, TPS7B6750-Q1 TPS7B6750A-Q1, TPS7B6750B-Q1 SLVSCB2A – OCTOBER 2013 – REVISED NOVEMBER 2013 www.ti.com DETAILED DESCRIPTION The TPS7B67xx-Q1 family of devices is an low-dropout linear regulator combined with an enable and reset function. The power-on-reset initializes when the output voltage, VO, exceeds 91.6% of the target value. The power-on reset delay is a function of the value set by an external capacitor on the DELAY pin before releasing the RST terminal high. Enable (EN) The enable pin is a high-voltage-tolerant terminal. A high input on EN actives the device and turns on the regulator. For self-bias applications, connect this input to the VIN terminal. Regulated Output (VOUT) The VOUT pin is the regulated output based on the required voltage. The output has current limitation. During initial power up, the regulator has a soft start incorporated to control the initial current through the pass element. In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. When the input voltage drops below the UVLO threshold, the regulator shuts down until the input voltage recovers above the minimum start-up level. Power-On-Reset (RESET) The power-on-reset is an output with an external pullup resistor to the regulated supply. The reset output remains low until the regulated VO exceeds approximately 90% of the set value and the power-on-reset delay has expired. The on-chip oscillator presets the delay. The regulated output falling below the 90% level asserts this output low after a short de-glitch time of approximately 180 µs (typical). Reset Delay Timer (DELAY) An external capacitor on this pin sets the timer delay before the reset pin is asserted high. The constant output current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. If this pin is open, the default delay time is 325 µs (typical). The reset pulse delay time td, is defined with the charge time of an external capacitor DELAY (see Equation 1). (1) The power-on-reset initializes when VO exceeds 90% of the programmed value. The power-on-reset delay is a function of the value set by an external capacitor on the DELAY pin before the RESET terminal is released high. Figure 20. Conditions to Activate RESET 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 TPS7B6750A-Q1 TPS7B6750B-Q1 |
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