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TPS40490MHRHDT Datasheet(PDF) 8 Page - Texas Instruments |
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TPS40490MHRHDT Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 38 page  TPS40490 SLVSCB4 – OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 48 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS TPS40490MHRHD: –12.5 12.5 VIN = 48 V, Rset = 31.6 kΩ, fSW = 1.15 MHz fsw_acc Switching frequency set accuracy % TPS40490MLRHD: –12.5 12.5 VIN = 12 V, Rset = 100 kΩ, fSW = 1.75 MHz VVALLEY Valley voltage 0.7 1 1.31 V TPS40490MLRHD: 5 V < VVIN ≤ 25 V 7.5 V/V KPWM PWM gain (VIN/VRAMP ) TPS40490MHRHD: 5 V < VVIN ≤ 60 V 20 V/V PWM AND DUTY CYCLE (PWM control) toff(MIN) Minimum off-time 5 V < VIN < 60 V 70 ns ERROR AMPLIFIER GBWP Gain bandwidth product 5 V < VIN < 60 V 40 MHz AOL Open loop gain VREF = 0.6 V 75 dB IIB Input bias current 100 nA IEAOP Output source current VVFB = 0 V, VREF = 0.6 V, output grounded 4.2 mA IEAOM Output sink current VVFB = 1 V, VREF = 0.6 V, output connected to 3-V supply 2.5 mA PROGRAMMABLE SOFT-START Soft-start source current at ISS VSS = 0.5 V 8.5 10.5 12.5 µA VSS < 0.5 V GATE DRIVERS High side VDR-0.6 VG Gate voltage V Low side VDR RHDHI High-side driver pull-up resistance CL = 1 nF, VDR = 5 V 0.7 Ω High-side driver pull-down RHDLO 0.35 Ω resistance RLDHI Low-side driver pull-up resistance 0.7 Ω RLDLO Low-side driver pull-down resistance 0.35 Ω tRC Drive rise time 5 ns tFC Drive fall time 5 ns DEAD TIME CONTROLLER (DTC) AND PROPAGATION DELAY DT3 DT2 DT1 T(ns) 0 0 1 7.5 Dead time range HDRV fall and tDT_H2L_EXT 0 1 1 18 ns LDRV rise 1 0 1 32 1 1 1 45 DT3 DT2 DT1 T(ns) 0 0 1 5 tDT_L2H_EXT HDRV rise and LDRV fall 0 1 1 18 ns 1 0 1 32 1 1 1 44 Dead time internal Measured dead time will be the highest of tDT_H2L_INT HDRV fall and LDRV rise 7.5 ns tDEAD_TIME_INT, tDEAD_TIME_EXT (Internal value fixed 001) Dead time internal Measured dead time will be the highest of tDT_L2H_INT HDRV rise and LDRV fall 5 ns tDEAD_TIME_INT, tDEAD_TIME_EXT (Internal value fixed 001) tDEAD_TIME_ACC Accuracy dead time setting Percentage of set time 001 setting –10% 10% tHPHL high turn-off propagation delay Falling gate voltage, 0 ns DTC time 25 ns tHPLH High turn-off propagation delay Rising gate voltage, 0 ns DTC time 25 ns tLPHL Low turn-off propagation delay Falling gate voltage, 0 ns DTC time 25 ns tLPLH Low turn-off propagation delay Rising gate voltage, 0 ns DTC time 25 ns Delay matching HS gate off to LS gate ON, 0 ns DTC time –4 0 4 ns 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS40490 |
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