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ADC083000CIYB Datasheet(PDF) 9 Page - Texas Instruments |
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ADC083000CIYB Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 48 page  I / O GND V A TO INTERNAL CIRCUITRY ADC083000 www.ti.com SNAS358N – JUNE 2006 – REVISED JULY 2009 PACKAGE THERMAL RESISTANCE Package θJA θJC (Top of Package) θJ-PAD (Thermal Pad) 128-Lead Exposed Pad HLQFP 26°C / W 10°C / W 2.8°C / W CONVERTER ELECTRICAL CHARACTERISTICS The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 820mVP-P, CL = 10 pF, Differential a.c. coupled Sinewave Input Clock, fCLK = 1.5GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential, after calibration. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (1) (2) Units Symbol Parameter Conditions Typical(3) Limits (3) (Limits) STATIC CONVERTER CHARACTERISTICS DC Coupled, 1MHz Sine INL Integral Non-Linearity (Best fit) ±0.35 ±0.9 LSB (max) Wave Over Ranged DC Coupled, 1MHz Sine DNL Differential Non-Linearity ±0.20 ±0.6 LSB (max) Wave Over Ranged Resolution with No Missing Codes 8 Bits VOFF Offset Error -0.20 LSB VOFF_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV PFSE Positive Full-Scale Error (4) −1.6 ±25 mV (max) NFSE Negative Full-Scale Error (4) −1.00 ±25 mV (max) FS_ADJ Full-Scale Adjustment Range Extended Control Mode ±20 ±15 %FS DYNAMIC CONVERTER CHARACTERISTICS FPBW Full Power Bandwidth 3 GHz Errors/Sa Word Error Rate 10-18 mple Gain Flatness 0.0 to -1.0 dBFS 50 to 950 MHz fIN = 373 MHz, VIN = FSR − 7.2 6.8 Bits (min) 0.5 dB fIN = 748 MHz, VIN = FSR − ENOB Effective Number of Bits 7.0 6.6 Bits (min) 0.5 dB fIN = 1498 MHz, VIN = FSR − 6.5 Bits 0.5 dB (1) The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device. (2) To ensure accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally, achieving rated performance requires that the backside exposed pad be well grounded. (3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). (4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error. Copyright © 2006–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADC083000 |
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