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ADS8405IPFBR Datasheet(PDF) 6 Page - Texas Instruments |
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ADS8405IPFBR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 29 page  www.ti.com TIMING CHARACTERISTICS ADS8405 SLAS427 – DECEMBER 2004 All specifications typical at –40 °C to 85°C, +VA = 5 V, +VBD = 3 V(1)(2)(3) PARAMETER MIN TYP MAX UNIT tCONV Conversion time 500 650 ns tACQ Acquisition time 150 ns tpd1 CONVST low to BUSY high 50 ns tpd2 Propagation delay time, end of conversion to BUSY low 10 ns tw1 Pulse duration, CONVST low 20 ns tsu1 Setup time, CS low to CONVST low 0 ns tw2 Pulse duration, CONVST high 20 ns CONVST falling edge jitter 10 ps tw3 Pulse duration, BUSY signal low Min(tACQ) ns tw4 Pulse duration, BUSY signal high 610 ns Hold time, first data bus transition (RD low, or CS low for read cycle, th1 40 ns or BYTE input changes) after CONVST low td1 Delay time, CS low to RD low (or BUSY low to RD low when CS = 0) 0 ns tsu2 Setup time, RD high to CS high 0 ns tw5 Pulse duration, RD low 50 ns ten Enable time, RD low (or CS low for read cycle) to data valid 30 ns td2 Delay time, data hold from RD high 0 ns td3 Delay time, BYTE rising edge or falling edge to data valid 2 30 ns tw6 Pulse duration, RD high 20 ns tw7 Pulse duration, CS high 20 ns Hold time, last RD (or CS for read cycle ) rising edge to CONVST th2 50 ns falling edge tsu3 Setup time, BYTE transition to RD falling edge 0 ns th3 Hold time, BYTE transition to RD falling edge 0 ns tdis Disable time, RD high (CS high for read cycle) to 3-stated data bus 30 ns td5 Delay time, end of conversion to MSB data valid 20 ns Byte transition setup time, from BYTE transition to next BYTE tsu4 50 ns transition td6 Delay time, CS rising edge to BUSY falling edge 50 ns td7 Delay time, BUSY falling edge to CS rising edge 50 ns Setup time, from the falling edge of CONVST (used to start the valid conversion) to the next falling edge of CONVST (when CS = 0 and tsu(AB) 70 500 ns CONVST used to abort) or to the next falling edge of CS (when CS is used to abort) Setup time, falling edge of CONVST to read valid data (MSB) from tsu5 MAX(tCONV) + MAX(td5) ns current conversion Hold time, data (MSB) from previous conversion hold valid from th4 MIN(tCONV) ns falling edge of CONVST (1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. (3) All timings are measured with 10-pF equivalent loads on all data bits and BUSY pins. 6 |
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