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TPS65581

SLVSC38A – OCTOBER 2013 – REVISED NOVEMBER 2013

www.ti.com

OVERVIEW

The TPS65581 is a 1.5A, 2.5A, 1.5A triple synchronous step-down (buck) converter with two integrated N-

channel MOSFETs for each channel. It operates using Advanced D-CAP2™ control mode. The fast transient

response of Advanced D-CAP2™ control reduces the required output capacitance to meet a specific level of

performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and

special polymer types.

DETAILED DESCRIPTION

PWM Operation

The main control loop of the TPS65581 is a fixed switching frequency pulse width modulation (PWM) controller

that supports a proprietary advanced D-CAP2™ mode control. Advanced D-CAP2™ mode control combines

constant switching frequency with an internal compensation circuit and low external component count

configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the

output.

Auto-Skip Eco-mode™ Control

The TPS65581 is designed with Auto-Skip Eco-mode™ to increase light load efficiency. As the output current

decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its

rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous

conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load

current further decreases the converter run into discontinuous conduction mode. The transition point to the light

(1)

PWM Frequency and Adaptive On-Time Control

TPS65581 uses a advanced D-CAP2 mode control scheme and have a dedicated on board oscillator. The

device runs with fixed frequency of 700 kHz.

Soft Start and Pre-Biased Soft Start

The TPS65581 has an internal, 1.2 ms, soft-start for each channel. When the ENx pin becomes high, an internal

DAC begins ramping up the reference voltage to the PWM comparator. Smooth control of the output voltage is

maintained during start up.

The device contains a unique circuit to prevent current from being pulled from the output during startup if the

output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start

starting the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a

cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.

This scheme prevents the initial sinking of the pre-biased output, and ensures that the output voltage (VOx)

starts and ramps up smoothly into regulation from pre-biased startup to normal mode operation.

Current Protection

The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit and

using HICCUP mode overcurrent protection. The switch current is monitored by measuring the low-side FET

switch voltage between the SWx pin and PGNDx. This voltage is proportional to the switch current and the on-

resistance of the FET. To improve accuracy, the voltage sensing is temperature compensated.

low side FET is above the voltage proportional to the current limit, the converter keeps the low-side switch on

until the measured voltage falls below the voltage corresponding to the current limit and a new switching cycle

begins. In subsequent switching cycles, the on-time is set to the value determined for CCM and the current is

monitored in the same manner.

8

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