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AD9219-65EBZ Datasheet(PDF) 1 Page - Analog Devices |
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AD9219-65EBZ Datasheet(HTML) 1 Page - Analog Devices |
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1 / 56 page  Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC Data Sheet AD9219 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. FEATURES 4 ADCs integrated into 1 package 94 mW ADC power per channel at 65 MSPS SNR = 60 dB (to Nyquist) ENOB = 9.7 bits SFDR = 78 dBc (to Nyquist) Excellent linearity DNL = ±0.2 LSB (typical) INL = ±0.3 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 315 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment GENERAL DESCRIPTION The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital con- verter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. FUNCTIONAL BLOCK DIAGRAM SERIAL LVDS REF SELECT +– AD9219 AGND VIN – A VIN + A VIN – B VIN + B VIN – D VIN + D VIN – C VIN + C SENSE VREF AVDD DRVDD 10 10 10 10 PDWN REFT REFB D – A D + A D – B D + B D – D D + D D – C D + C FCO– FCO+ DCO+ DCO– CLK+ DRGND CLK– SERIAL PORT INTERFACE CSB SCLK/DTP SDIO/ODM RBIAS SERIAL LVDS SERIAL LVDS SERIAL LVDS PIPELINE ADC PIPELINE ADC PIPELINE ADC PIPELINE ADC DATA RATE MULTIPLIER 0.5V Figure 1. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI). The AD9219 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. Small Footprint. Four ADCs are contained in a small, space- saving package. 2. Low power of 94 mW/channel at 65 MSPS. 3. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. 4. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. 5. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9228 (12-bit), and AD9259 (14-bit). |
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