TPS92411, TPS92411P

SLUSBQ6 – OCTOBER 2013

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

terminal (unless otherwise noted).

VALUE

UNIT

MIN

MAX

Supply voltage

VIN

–0.3

105

V

Switch voltage

DRAIN

-0.3

105

Junction temperature

-40

165

ºC

Storage temperature range

-65

150

(HBM) QSS 009-105 (JESD22-A114A)

1

kV

Electrostatic Discharge

Field Induced Charged Device Model (FIDCM)

250

V

THERMAL INFORMATION

TPS92411

SOT-23

PSOP

UNITS

5 PINS

8 PINS

209.8

58.6

125.2

72

38

39.1

°C/W

15.6

21.6

37.1

39.1

N/A

15

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specified JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range (unless otherwise noted)

MIN

TYP

MAX

UNIT

TPS92411P

7.5

94

VIN

Input voltage

V

TPS92411

7.5

100

Operating junction temperature

–40

25

150

°C

DBV (SOT23-5)

100

200

Switch drain (DRAIN) to source (VS) current

mA

DDA (SO-8 Power-Pad)

175

350

2

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