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TS68C429A Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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TS68C429A Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 46 page  4 0848E–HIREL–02/08 TS68C429A e2v semiconductors SAS 2008 2. Package See “Package Mechanical Data” on page 41 and “Terminal Connections” on page 42. Table 2-1. Signal Description Pin Name Type Function A0-8 I Address bus. The address bus is used to select one of the internal registers during a processor read or write cycle. D0-15 I/O This bi-directional bus is used to receive data from or transmit data to an internal register during a processor read or write cycle. During an interrupt acknowledge cycle, the vector number is given on the lower data bus (D0 - D7). CS I Chip select (active low). This input is used to select the chip for internal register access. LDS I Lower data strobe. This input (active low) validates lower data during R/W access (D0-D7). UDS I Upper data strobe. This input (active low) validates upper data during R/W access (D8-D15). R/W I Read/write. This input defines a data transfer as a read (high) or a write (low) cycle. DTACK O Data transfer acknowledge. If the bus cycle is a processor read, the chip asserts DTACK to indicate that the information on the data bus is valid. If the bus cycle is a processor write, DTACK acknowledges the acceptance of the data by the MRT. DTACK will be asserted during chip select access (CS asserted) or interrupt acknowledge cycle (IACKTX or IACKRK asserted). IRQTX O Interrupt transmit request. This open drain output signals to the processor that an interrupt is pending from the transmission part of the MRT. There are 6 causes that can generate an interrupt request (2 per channel: FIFO empty and end of transmission). IACKTX I Interrupt transmit acknowledge. If IRQTX is active, the MRT will begin an interrupt acknowledge cycle. The MRT will generate a vector number to the processor which is the highest priority channel requesting interrupt service. IEITX I Interrupt transmit enable in. This input, together with IEOTX signal, provides a daisy chained interrupt structure for a vectored scheme. IEITX (active low) indicates that no higher priority device is requesting interrupt service. IEOTX O Interrupt transmit enable out. This output, together with IEITX signal, provides a daisy chained interrupt structure for a vectored interrupt scheme. IEOTX (active low) indicates to lower priority devices that neither the TS68C429A nor any highest priority peripheral is requesting an interrupt. IRQRX O Interrupt transmit request. This open drain output signals to the processor that an interrupt is pending from the receiving part of the chip. There are 9 causes that can generate an interrupt request (1 per channel: valid message received, and 1 for bad parity on a received message). IACKRX I Interrupt receive acknowledge. Same function as IACKTX but for receiver part. IEIRX I Interrupt receive enable in. Same function as IEITX but for receiver part. IEORX I Interrupt receive enable out. Same function as IEOTX but for receiver part. TX1H O Transmission “1” line of the channel 1. TX1L O Transmission “0” line of the channel 1. TX2H O Transmission “1” line of the channel 2. TX2L O Transmission “0” line of the channel 2. TX3H O Transmission “1” line of the channel 3. TX3L O Transmission “0” line of the channel 3. RX1H I Receiving “1” line of the channel 1. |
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