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ADP1713AUJZ-0.75R7 Datasheet(PDF) 10 Page - Analog Devices |
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ADP1713AUJZ-0.75R7 Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page ADP1712/ADP1713/ADP1714 Rev. A | Page 10 of 16 THEORY OF OPERATION The ADP1712/ADP1713/ADP1714 are low dropout linear regula- tors that use an advanced, proprietary architecture to provide high power supply rejection ratio (PSRR) and excellent line and load transient response with just a small 2.2 μF ceramic output capac- itor. All devices operate from a 2.5 V to 5.5 V input rail and provide up to 300 mA of output current. Incorporating a novel scaling architecture, ground current is very low when driving light loads. Ground current in the shutdown mode is typically less than 1 μA. REFERENCE CURRENT LIMIT THERMAL PROTECT SHUTDOWN AND UVLO GND OUT SS/ ADJ/ BYP/ TRK IN EN Figure 25. Internal Block Diagram Internally, the ADP1712/ADP1713/ADP1714 each consist of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback volt- age from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, which allows more current to pass and increases the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage. The ADP1712 is available in two versions, one with a fixed output voltage and one with an adjustable output voltage. The fixed output voltage is set internally to one of sixteen values between 0.75 V and 3.3 V, using an internal feedback network. The adjustable output voltage can be set to between 0.8 V and 5.0 V by an external voltage divider connected from OUT to ADJ. The ADP1713 and ADP1714 are available in fixed output voltage options only. The ADP1712 fixed version allows an external soft-start capacitor to be connected between the SS pin and GND, which controls the output voltage ramp during startup. The ADP1713 allows a reference bypass capacitor to be connected between the BYP pin and GND, which reduces output voltage noise and improves power supply rejection. The ADP1714 features a track pin, which allows the output voltage to follow the voltage at the TRK pin. A logic on the EN pin determines if the output is active. When EN is high, the output is on, and when EN is low, the output is off. SOFT-START FUNCTION (ADP1712) For applications that require a controlled startup, the ADP1712 provides a programmable soft-start function. Programmable soft start is useful for reducing inrush current upon startup and for pro- viding voltage sequencing. To implement soft start, connect a small ceramic capacitor from SS to GND. Upon startup, a 1.2 μA current source charges this capacitor. The ADP1712 start-up output voltage is limited by the voltage at SS, providing a smooth ramp up to the nominal output voltage. The soft-start time is calculated by TSS = VREF × (CSS/ISS) (1) where: TSS is the soft-start period. VREF is the 0.8 V reference voltage. CSS is the soft-start capacitance from SS to GND. ISS is the current sourced from SS (1.2 μA). When the ADP1712 is disabled (using EN), the soft-start capacitor is discharged to GND through an internal 100 Ω resistor. TIME (4ms/DIV) 1 2 EN OUT VIN = 5V VOUT = 3.3V COUT = 2.2μF CSS = 22nF ILOAD = 300mA Figure 26. OUT Ramp-Up with External Soft-Start Capacitor The ADP1712 adjustable version, ADP1713, and ADP1714 have no pins for soft start, so the function is switched to an internal soft-start capacitor. This sets the soft-start ramp-up period to approximately 24 μs. TIME (20µs/DIV) 1 2 EN OUT VIN = 5V VOUT = 1.6V COUT = 2.2μF ILOAD = 10mA Figure 27. OUT Ramp-Up with Internal Soft-Start |
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