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24LC21AT-I-P Datasheet(PDF) 4 Page - Microchip Technology |
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24LC21AT-I-P Datasheet(HTML) 4 Page - Microchip Technology |
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4 / 18 page  24LC21A DS21160F-page 4 2003 Microchip Technology Inc. 2.0 FUNCTIONAL DESCRIPTION The 24LC21A is designed to comply to the DDC Standard proposed by VESA (Figure 3-3) with the exception that it is not Access.bus capable. It operates in two modes, the Transmit-only mode and the Bidirectional mode. There is a separate 2-wire protocol to support each mode, each having a separate clock input but sharing a common data line (SDA). The device enters the Transmit-only mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high-to-low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bidirectional mode and look for its control byte to be sent by the master. If it detects its control byte, it will stay in the Bidirectional mode. Otherwise, it will revert to the Transmit-only mode after it sees 128 VCLK pulses. 2.1 Transmit-Only Mode The device will power-up in the Transmit-only mode at address 00H. This mode supports a unidirectional 2-wire protocol for continuous transmission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the Transmit-only mode (Section 2.2 “Initialization Pro- cedure”). In this mode, data is transmitted on the SDA pin in 8-bit bytes, with each byte followed by a ninth, null bit (Figure 2-1). The clock source for the Transmit- only mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted Most Significant bit first. Each byte within the memory array will be output in sequence. After address 7Fh in the memory array is transmitted, the internal address pointers will wrap around to the first memory location (00h) and continue. The Bidirectional mode Clock (SCL) pin must be held high for the device to remain in the Transmit-only mode. 2.2 Initialization Procedure After VCC has stabilized, the device will be in the Transmit-only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal sychronization. During this period, the SDA pin will be in a high-impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit in address 00h. (Figure 2-2). FIGURE 2-1: TRANSMIT-ONLY MODE FIGURE 2-2: DEVICE INITIALIZATION SCL SDA VCLK Tvaa Tvaa Bit 1 (LSB) Null Bit Bit 1 (MSB) Bit 7 Tvlow Tvhigh Tvaa Tvaa Bit 8 Bit 7 High-impedance for 9 clock cycles Tvpu 12 8 9 10 11 SCL SDA VCLK Vcc |
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