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Motorola TMOS Power MOSFET Transistor Device Data

Designer's™ Data Sheet

TMOS V™

Power Field Effect Transistor

N–Channel Enhancement–Mode Silicon Gate

TMOS V is a new technology designed to achieve an on–resis-

tance area product about one–half that of standard MOSFETs. This

new technology more than doubles the present cell density of our

50 and 60 volt TMOS devices. Just as with our TMOS E–FET

designs, TMOS V is designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high

speed switching applications in power supplies, converters and

power motor controls, these devices are particularly well suited for

bridge circuits where diode speed and commutating safe operating

areas are critical and offer additional safety margin against

unexpected voltage transients.

New Features of TMOS V

• On–resistance Area Product about One–half that of Standard

MOSFETs with New Low Voltage, Low RDS(on) Technology

• Faster Switching than E–FET Predecessors

Features Common to TMOS V and TMOS E–FETS

• Avalanche Energy Specified

• IDSS and VDS(on) Specified at Elevated Temperature

• Static Parameters are the Same for both TMOS V and TMOS E–FET

Rating

Symbol

Value

Unit

Drain–Source Voltage

VDSS

60

Vdc

Drain–Gate Voltage (RGS = 1.0 MΩ)

VDGR

60

Vdc

Gate–Source Voltage — Continuous

VGS

VGSM

± 20

± 25

Vdc

Vpk

Drain Current — Continuous

°C

ID

ID

IDM

52

41

182

Adc

Apk

Total Power Dissipation

Derate above 25

°C

PD

188

1.25

Watts

W/

°C

Operating and Storage Temperature Range

TJ, Tstg

– 55 to 175

°C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 Ω)

EAS

406

mJ

Thermal Resistance — Junction to Case

R

θJC

R

θJA

0.8

62.5

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

″ from case for 10 seconds

TL

260

°C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

Order this document

by MTP52N06V/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MTP52N06V

TMOS POWER FET

52 AMPERES

60 VOLTS

RDS(on) = 0.022 OHM

Motorola Preferred Device

CASE 221A–06, Style 5

TO–220AB

TM

D

S

G

© Motorola, Inc. 1996