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34LC02T-I Datasheet(PDF) 6 Page - Microchip Technology |
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34LC02T-I Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 32 page  34AA02/34LC02 DS22029D-page 6 © 2008 Microchip Technology Inc. 2.0 FUNCTIONAL DESCRIPTION The 34XX02 has two Software Write-Protect features that allow you to protect half of the array from being written (Addresses 00h-7Fh). One command, Software Write-Protect (SWP) will prevent writes to half of the array and is resettable by using the Clear Software Write-Protect (CSWP) command. The other command is Permanent Software Write-Protect (PSWP), which is not resettable and will permanently lock half the array from being written to. The device still has an external pin (WP) that allows you to protect the entire array if so desired. The 34XX02 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data, as a receiver. The bus has to be controlled by a master device, which generates the Serial Clock (SCL), controls the bus access and gener- ates the Start and Stop conditions, while the 34XX02 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 Bus Not Busy (A) Both data and clock lines remain high. 3.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 3.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 3.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between the Start and Stop conditions is determined by the master device and is, theoretically, unlimited; although only the last sixteen will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first-in, first-out (FIFO) fashion. 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge after the reception of each byte. Exceptions to this rule relating to software write protection are described in Section 7.0 “Write Protec- tion”. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end-of- data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (34XX02) will leave the data line high to enable the master to generate the Stop condition. Note: The 34XX02 does not generate any Acknowledge bits if an internal programming cycle is in progress. |
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