MCP6S92 datasheet(3/40 Pages) MICROCHIP

Part #	MCP6S92

Description	Single-Ended, Rail-to-Rail I/O, Low-Gain PGA

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Manufacturer	MICROCHIP [Microchip Technology]

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 2004 Microchip Technology Inc.

DS21908A-page 3

MCP6S91/2/3

Ladder Resistance

RLAD

3.4

4.9

6.4

k

Ω

(Note 1)

Ladder Resistance across

Temperature

∆R

LAD/∆TA

—+0.028

—

%/°C

TA = -40°C to +125°C (Note 1)

Amplifier Output

DC Output Non-linearity G = +1

VONL

—

±0.18

—

% of FSR VOUT ≈ 0.3V to VDD − 0.3V, VDD =5.0V

G

≥ +2

VONL

—

±0.050

—

% of FSR VOUT ≈ 0.3V to VDD − 0.3V, VDD =5.0V

Maximum Output Voltage Swing

VOH_ANA,

VOL_ANA

VSS + 20

—

VDD – 100

mV

G

≥ +2; 0.5V output overdrive

VSS + 60

—

VDD – 60

G

≥ +2; 0.5V output overdrive,

VREF = VDD/2

Short Circuit Current

ISC

—±25

—

mA

Power Supply

Supply Voltage

VDD

2.5

—

5.5

V

Minimum Valid Supply Voltage

VDD_VAL

—

0.4

2.0

V

Register data still valid

Quiescent Current

IQ

0.4

1.0

1.6

mA

IO = 0 (Note 3)

Quiescent Current, Shutdown

Mode

IQ_SHDN

—30

—

pA

IO = 0 (Note 3)

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL =10 kΩ to VDD/2, SI and SCK are tied low and CS is tied high.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Note

1:

RLAD (RF+RG in Figure 4-1) connects VREF, VOUT and the inverting input of the internal amplifier. The MCP6S92 has

VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is

recommended that the MCP6S92’s VSS pin be tied directly to ground to avoid noise problems.

2:

The MCP6S92’s VIVR and VIVR_REF are not tested in production; they are set by design and characterization.

3:

IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents.

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