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HEF4027BT Datasheet(PDF) 8 Page - NXP Semiconductors |
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HEF4027BT Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 14 page HEF4027B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 9 — 18 November 2011 8 of 14 NXP Semiconductors HEF4027B Dual JK flip-flop VOH and VOL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Fig 6. Waveforms showing pulse widths and recovery times 001aae597 SD INPUT VI 0 V VI 0 V VI 0 V VOH VOL CD INPUT CP INPUT tW tW VM VM VM Q OUTPUT trec trec Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 7. Test circuit VDD VI VO 001aag182 DUT CL RT G Table 10. Test data Supply voltage Input Load VDD VI tr, tf CL 5 V to 15 V VSS or VDD 20 ns 50 pF |
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